src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl
index 82cbad63..81c2432 100644
--- a/src/soc/intel/alderlake/acpi/tcss.asl
+++ b/src/soc/intel/alderlake/acpi/tcss.asl
@@ -511,7 +511,7 @@
TACK, 1, /* [16:16] IOM Acknowledge bit */
DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */
/* display is OFF, clear otherwise */
- Offset(0x70), /* Pyhsical addr is offset 0x70. */
+ Offset(0x70), /* Physical addr is offset 0x70. */
IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */
IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
}
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index 6a71900..f6b337c 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -18,7 +18,7 @@
Offset(0xB4),
BGSM, 32, /* Base of Graphics Stolen Memory */
Offset(0xBC),
- TLUD, 32, /* Top of Low Useable DRAM */
+ TLUD, 32, /* Top of Low Usable DRAM */
}
}
@@ -58,7 +58,7 @@
* PCI MMIO Region (TOLUD - PCI extended base MMCONF)
* This assumes that MMCONF is placed after PCI config space,
* and that no resources are allocated after the MMCONF region.
- * This works, sicne MMCONF is hardcoded to 0xe00000000.
+ * This works, since MMCONF is hardcoded to 0xe00000000.
*/
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
NonCacheable, ReadWrite,
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 1c92b89..c4d7977 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -119,7 +119,7 @@
/*
* Poll for bit 8 to check if PCODE has completed its action
- * in reponse to BIOS Reset complete.
+ * in response to BIOS Reset complete.
* We wait here till 1 ms for the bit to get set.
*/
stopwatch_init_msecs_expire(&sw, 1);
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index e5c003a..dca95e3 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -136,7 +136,7 @@
bool "Use a binary refcode blob instead of native ModPHY init"
default n
help
- Use the ChromeBook refcode to intitialize high-speed PHYs instead of
+ Use the ChromeBook refcode to initialize high-speed PHYs instead of
native code.
if HAVE_REFCODE_BLOB
diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index b7ddee4..76d532b5 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -93,7 +93,7 @@
if (fsp_reserved_memory_area) {
fsp_res_base_k = RES_IN_KiB((unsigned int)fsp_reserved_memory_area);
} else {
- /* If no FSP reserverd area */
+ /* If no FSP reserved area */
fsp_res_base_k = tseg_base_k;
}
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index fbd7aea..f02e810 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -23,7 +23,7 @@
Broadwell can either start verstage in a separate stage
right after the bootblock has run or it can start it
after romstage for compatibility reasons.
- Broadwell however uses a mrc.bin to initialse memory which
+ Broadwell however uses a mrc.bin to initialize memory which
needs to be located at a fixed offset. Therefore even with
a separate verstage starting after the bootblock that same
binary is used meaning a jump is made from RW to the RO region
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index b8dfafd..774b526 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -436,7 +436,7 @@
*
* In general descriptor provides option to set default cpu flex ratio.
* Default cpu flex ratio is 0 ensures booting with non-turbo max frequency.
- * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0.
+ * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0.
*
* Only override CPU flex ratio if don't want to boot with non-turbo max.
*/
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index 56e3336..ad987dd 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -41,7 +41,7 @@
# $(3) is file type, efi for test names (all .EFI files under $(MMA_BLOBS_PATH)/tests )
# , mma for test param (all .BIN files under $(MMA_BLOBS_PATH)/configs/<test name>)
#
-# $(MMA_BLOBS_PATH)/tests/<testX>.efi has coresponding test params
+# $(MMA_BLOBS_PATH)/tests/<testX>.efi has corresponding test params
# at $(MMA_BLOBS_PATH)/configs/<testX>/<XYZ>.bin
#
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index f0c3149..cac7854 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -545,7 +545,7 @@
/*
* Calculate the SF Mask 1:
- * 1. Calcuate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0]
+ * 1. Calculate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0]
* 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: SFWayCnt = SFWayCnt / 2
* 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - IA32_CR_SF_QOS_MASK_2
*/
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c
index 843071e..93de2ec 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi.c
@@ -325,7 +325,7 @@
"Only 32MiB windows are supported for extended BIOS!");
#endif
- /* Confgiure DMI Source decode for Extended BIOS Region */
+ /* Configure DMI Source decode for Extended BIOS Region */
if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE,
soc_get_spi_dmi_destination_id()) == CB_ERR)
return;
diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h
index 97d63af..c07c96c 100644
--- a/src/soc/intel/common/block/include/intelblocks/tcss.h
+++ b/src/soc/intel/common/block/include/intelblocks/tcss.h
@@ -130,7 +130,7 @@
struct tcss_mux_info {
bool dp; /* DP connected */
bool usb; /* USB connected */
- bool cable; /* Activ/Passive Cable */
+ bool cable; /* Active/Passive Cable */
bool polarity; /* polarity of connected device */
bool hpd_lvl; /* HPD Level assert */
bool hpd_irq; /* HPD IRQ assert */
diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig
index aaf4479..e3978e2 100644
--- a/src/soc/intel/common/block/pmc/Kconfig
+++ b/src/soc/intel/common/block/pmc/Kconfig
@@ -17,7 +17,7 @@
bool
help
Select this on platforms where the PMC device is discoverable
- when scanning busses.
+ when scanning buses.
config SOC_INTEL_COMMON_BLOCK_PMC_EPOC
bool
diff --git a/src/soc/intel/common/block/usb4/Kconfig b/src/soc/intel/common/block/usb4/Kconfig
index d4e1c25..bc1eb19 100644
--- a/src/soc/intel/common/block/usb4/Kconfig
+++ b/src/soc/intel/common/block/usb4/Kconfig
@@ -25,4 +25,4 @@
depends on SOC_INTEL_COMMON_BLOCK_USB4
select PCIEXP_HOTPLUG
help
- Enable USB4 PCIe resources for reserving hotplug busses and memory.
+ Enable USB4 PCIe resources for reserving hotplug buses and memory.
diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h
index 512f7f5..fdb1028 100644
--- a/src/soc/intel/denverton_ns/include/soc/pmc.h
+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h
@@ -11,7 +11,7 @@
#define MASK_PMC_ACPI_BASE 0xfffc
#define PMC_ACPI_CNT 0x44
#define PMC_ACPI_CNT_PWRM_EN (1 << 8) /* PWRM enable */
-#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI eanble */
+#define PMC_ACPI_CNT_ACPI_EN (1 << 7) /* ACPI enable */
#define PMC_ACPI_CNT_SCIS ((1 << 2) | (1 << 1) | (1 << 0)) /* SCI IRQ select \
*/
#define PMC_ACPI_CNT_SCIS_MASK 0x07
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 2d09f51..1a9bfef 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -222,7 +222,7 @@
select COMMONLIB_STORAGE
select SDHCI_CONTROLLER
help
- Read block 0 from each parition of the storage device. User
+ Read block 0 from each partition of the storage device. User
must also enable one or both of COMMONLIB_STORAGE_SD or
COMMONLIB_STORAGE_MMC.
diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h
index 40e823f..7308712 100644
--- a/src/soc/intel/quark/chip.h
+++ b/src/soc/intel/quark/chip.h
@@ -87,7 +87,7 @@
uint8_t DramDensity;
uint8_t tCL; /* DRAM CAS Latency in clocks */
- /* ECC scrub interval in miliseconds 1..255 (0 works as feature
+ /* ECC scrub interval in milliseconds 1..255 (0 works as feature
* disable)
*/
uint8_t EccScrubInterval;
diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h
index c7db8d5..e4015a2 100644
--- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h
+++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h
@@ -55,7 +55,7 @@
//
//
-// DEVICE 0 (Memroy Controller Hub)
+// DEVICE 0 (Memory Controller Hub)
//
#define MC_BUS PCI_BUS_NUMBER_QNC
#define MC_DEV 0x00
@@ -729,7 +729,7 @@
#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset
#define R_QNC_PCIE_SLCTL 0x58 //~ 59h
#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable
-#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable
+#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable
#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable
#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh
#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c
index 8671398..604561a 100644
--- a/src/soc/intel/quark/reg_access.c
+++ b/src/soc/intel/quark/reg_access.c
@@ -69,7 +69,7 @@
{
uint32_t offset;
- /* Convert from MTRR index to host brigde offset (Datasheet 12.7.2) */
+ /* Convert from MTRR index to host bridge offset (Datasheet 12.7.2) */
if (index == MTRR_CAP_MSR)
offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP;
else if (index == MTRR_DEF_TYPE_MSR)
diff --git a/src/soc/intel/quark/spi_debug.c b/src/soc/intel/quark/spi_debug.c
index b249065..a6b5e69 100644
--- a/src/soc/intel/quark/spi_debug.c
+++ b/src/soc/intel/quark/spi_debug.c
@@ -79,7 +79,7 @@
printk(BIOS_DEBUG, "0x%08x: BIOS Base Address\n", ctrlr->bbar);
/* Display the protection ranges */
- printk(BIOS_DEBUG, "BIOS Protected Range Regsiters\n");
+ printk(BIOS_DEBUG, "BIOS Protected Range Registers\n");
for (index = 0; index < ARRAY_SIZE(ctrlr->pbr); index++) {
status = ctrlr->pbr[index];
printk(BIOS_DEBUG, " %d: 0x%08x: 0x%08x - 0x%08x %s\n",
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 7e06ffa..72c5e47 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -36,7 +36,7 @@
#define CPUID_6_EAX_ISST (1 << 7)
/*
- * List of suported C-states in this processor.
+ * List of supported C-states in this processor.
*/
enum {
C_STATE_C0, /* 0 */
diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h
index 3d12861..dd28255 100644
--- a/src/soc/intel/skylake/include/soc/nhlt.h
+++ b/src/soc/intel/skylake/include/soc/nhlt.h
@@ -30,7 +30,7 @@
int nhlt_soc_add_dmic_array(struct nhlt *nhlt, int num_channels);
/*
- * Add nau88l25 headset codec on provided SSP link. Return 0 on succes, < 0
+ * Add nau88l25 headset codec on provided SSP link. Return 0 on success, < 0
* on error.
*/
int nhlt_soc_add_nau88l25(struct nhlt *nhlt, int hwlink);
diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl
index 9893833..2a71b31 100644
--- a/src/soc/intel/tigerlake/acpi/tcss.asl
+++ b/src/soc/intel/tigerlake/acpi/tcss.asl
@@ -511,7 +511,7 @@
TACK, 1, /* [16:16] IOM Acknowledge bit */
DPOF, 1, /* [17:17] Set 1 to indicate IOM, all the */
/* display is OFF, clear otherwise */
- Offset(0x70), /* Pyhsical addr is offset 0x70. */
+ Offset(0x70), /* Physical addr is offset 0x70. */
IMCD, 32, /* R_SA_IOM_BIOS_MAIL_BOX_CMD */
IMDA, 32 /* R_SA_IOM_BIOS_MAIL_BOX_DATA */
}
diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c
index ce0b1a6..579ebbc 100644
--- a/src/soc/intel/xeon_sp/util.c
+++ b/src/soc/intel/xeon_sp/util.c
@@ -168,7 +168,7 @@
unsigned int num_sockets;
/*
- * sort APIC ids in asending order to identify apicid ranges for
+ * sort APIC ids in ascending order to identify apicid ranges for
* each numa domain
*/
for (dev = all_devices; dev; dev = dev->next) {