soc/amd/phoenix/chip: use common data fabric domain resource code
Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.
BUG=b:283495475
TEST=Myst still boots and both the coreboot console and the kernel show
the expected PCI MMIO ranges being used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I425876c4ef470574e00e123d36101641240c98cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/phoenix/chip.c b/src/soc/amd/phoenix/chip.c
index ee2c7cc..1bbb1b5 100644
--- a/src/soc/amd/phoenix/chip.c
+++ b/src/soc/amd/phoenix/chip.c
@@ -28,10 +28,11 @@
};
struct device_operations phoenix_pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
+ .read_resources = amd_pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
- .scan_bus = pci_domain_scan_bus,
+ .scan_bus = amd_pci_domain_scan_bus,
.acpi_name = soc_acpi_name,
+ .acpi_fill_ssdt = amd_pci_domain_fill_ssdt,
};
static void soc_init(void *chip_info)