nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 6bb77b2..4563547 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -204,6 +204,7 @@
#define GET_ERR_CHANNEL(x) (x>>16)
static void program_timings(ramctr_timing * ctrl, int channel);
+static unsigned int get_mmio_size(void);
static const char *ecc_decoder[] = {
"inactive",
@@ -1086,7 +1087,7 @@
size_t tsegbasedelta, remapbase, remaplimit;
uint16_t ggc;
- mmiosize = 0x400;
+ mmiosize = get_mmio_size();
ggc = pci_read_config16(NORTHBRIDGE, GGC);
if (!(ggc & 2)) {
@@ -4384,6 +4385,24 @@
}
}
+#define DEFAULT_PCI_MMIO_SIZE 2048
+
+static unsigned int get_mmio_size(void)
+{
+ const struct device *dev;
+ const struct northbridge_intel_sandybridge_config *cfg = NULL;
+
+ dev = dev_find_slot(0, HOST_BRIDGE);
+ if (dev)
+ cfg = dev->chip_info;
+
+ /* If this is zero, it just means devicetree.cb didn't set it */
+ if (!cfg || cfg->pci_mmio_size == 0)
+ return DEFAULT_PCI_MMIO_SIZE;
+ else
+ return cfg->pci_mmio_size;
+}
+
void perform_raminit(int s3resume)
{
spd_raw_data spd[4];