commit 25f75b28e4e545eb2c42e4e201055661e57a90ca
author Furquan Shaikh <furquan@google.com> Mon Aug 29 22:51:41 2016 -0700
committer Martin Roth <martinroth@google.com> Tue Sep 13 17:21:02 2016 +0200
tree 486df3a3e3c18d9e268f8503a640bd3fc2dc502b
parent 823f1a9bbfc5daf72e5f2f76bf2034b250396d9d

northbridge/intel/gm45: transation away from device_t

Replace the use of the old device_t definition inside
northbridge/intel/gm45.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16402
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/northbridge/intel/gm45/igd.c

diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index dc0cc91..73f7651 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -30,9 +30,9 @@
 /* The PEG settings have to be set before ASPM is setup on DMI. */
 static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
-	const device_t peg_dev	= PCI_DEV(0, 1, 0);
-	const device_t igd_dev	= PCI_DEV(0, 2, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
+	const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0);
+	const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
 
 	u16 reg16;
 	u32 reg32;
@@ -110,7 +110,7 @@
 
 static void disable_igd(const sysinfo_t *const sysinfo)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
 
 	printk(BIOS_DEBUG, "Disabling IGD.\n");
 
@@ -131,7 +131,7 @@
 
 void init_igd(const sysinfo_t *const sysinfo)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
 
 	const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4);
 	if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
@@ -142,7 +142,7 @@
 
 void igd_compute_ggc(sysinfo_t *const sysinfo)
 {
-	const device_t mch_dev	= PCI_DEV(0, 0, 0);
+	const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
 
 	const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
 	if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))