blob: 4ea7ef10809eec2b68af7ad3adf5ccb2dea1861e [file] [log] [blame]
/* $NoKeywords:$ */
/**
* @file
*
* Register definitions
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 64732 $ @e \$Date: 2012-01-30 02:16:26 -0600 (Mon, 30 Jan 2012) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _GNBREGISTERSTN_H_
#define _GNBREGISTERSTN_H_
#define TYPE_D0F0 0x1
#define TYPE_D0F0x64 0x2
#define TYPE_D0F0x98 0x3
#define TYPE_D0F0xBC 0x4
#define TYPE_D0F0xE4 0x5
#define TYPE_DxF0 0x6
#define TYPE_DxF0xE4 0x7
#define TYPE_D0F2 0x8
#define TYPE_D0F2xF4 0x9
#define TYPE_D0F2xFC 0xa
#define TYPE_D18F1 0xb
#define TYPE_D18F2 0xc
#define TYPE_D18F3 0xd
#define TYPE_D18F4 0xe
#define TYPE_D18F5 0xf
#define TYPE_MSR 0x10
#define TYPE_D1F0 0x11
#define TYPE_GMM 0x12
#define TYPE_D18F2x9C_dct0 0x13
#define TYPE_D18F2x9C_dct0_mp0 0x14
#define TYPE_D18F2x9C_dct0_mp1 0x15
#define TYPE_D18F2x9C_dct1 0x16
#define TYPE_D18F2x9C_dct1_mp0 0x17
#define TYPE_D18F2x9C_dct1_mp1 0x18
#define TYPE_D18F2_dct0 0x19
#define TYPE_D18F2_dct1 0x1a
#define TYPE_D18F2_dct0_mp0 0x1b
#define TYPE_D18F2_dct0_mp1 0x1c
#define TYPE_D1F1 0x1d
#define TYPE_D18F2_dct1_mp0 0x1e
#define TYPE_D18F2_dct1_mp1 0x1f
#define TYPE_CGIND 0x20
#define TYPE_SMU_MSG 0x21
#ifndef WRAP_SPACE
#define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x))
#endif
#ifndef CORE_SPACE
#define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x))
#endif
#ifndef PHY_SPACE
#define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
#ifndef PIF_SPACE
#define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
#define L1_SEL_GFX 0
#define L1_SEL_GPPSB 1
#define L1_SEL_GBIF 2
#define L1_SEL_INTGEN 3
#define SMU_MSG_TYPE TYPE_SMU_MSG
#define SMC_MSG_FIRMWARE_AUTH 0
#define SMC_MSG_HALT 1
#define SMC_MSG_PHY_LN_OFF 2
#define SMC_MSG_PHY_LN_ON 3
#define SMC_MSG_DDI_PHY_OFF 4
#define SMC_MSG_DDI_PHY_ON 5
#define SMC_MSG_CASCADE_PLL_OFF 6
#define SMC_MSG_CASCADE_PLL_ON 7
#define SMC_MSG_PWR_OFF_x16 8
#define SMC_MSG_CONFIG_LCLK_DPM 9
#define SMC_MSG_FLUSH_DATA_CACHE 10
#define SMC_MSG_FLUSH_INSTRUCTION_CACHE 11
#define SMC_MSG_CONFIG_VPC_ACCUMULATOR 12
#define SMC_MSG_CONFIG_BAPM 13
#define SMC_MSG_CONFIG_TDC_LIMIT 14
#define SMC_MSG_CONFIG_LPMx 15
#define SMC_MSG_CONFIG_HTC_LIMIT 16
#define SMC_MSG_CONFIG_THERMAL_CNTL 17
#define SMC_MSG_CONFIG_VOLTAGE_CNTL 18
#define SMC_MSG_CONFIG_TDP_CNTL 19
#define SMC_MSG_EN_PM_CNTL 20
#define SMC_MSG_DIS_PM_CNTL 21
#define SMC_MSG_CONFIG_NBDPM 22
#define SMC_MSG_CONFIG_LOADLINE 23
#define SMC_MSG_ADJUST_LOADLINE 24
#define SMC_MSG_RECONFIGURE 25
#define SMC_MSG_PCIE_PLLSWITCH 27
#define SMC_MSG_ENABLE_BAPM 32
#define SMC_MSG_DISABLE_BAPM 33
// **** D0F0x00 Register Definition ****
// Address
#define D0F0x00_ADDRESS 0x0
// Type
#define D0F0x00_TYPE TYPE_D0F0
// Field Data
#define D0F0x00_VendorID_OFFSET 0
#define D0F0x00_VendorID_WIDTH 16
#define D0F0x00_VendorID_MASK 0xffff
#define D0F0x00_DeviceID_OFFSET 16
#define D0F0x00_DeviceID_WIDTH 16
#define D0F0x00_DeviceID_MASK 0xffff0000
/// D0F0x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x00_STRUCT;
// **** D0F0x04 Register Definition ****
// Address
#define D0F0x04_ADDRESS 0x4
// Type
#define D0F0x04_TYPE TYPE_D0F0
// Field Data
#define D0F0x04_IoAccessEn_OFFSET 0
#define D0F0x04_IoAccessEn_WIDTH 1
#define D0F0x04_IoAccessEn_MASK 0x1
#define D0F0x04_MemAccessEn_OFFSET 1
#define D0F0x04_MemAccessEn_WIDTH 1
#define D0F0x04_MemAccessEn_MASK 0x2
#define D0F0x04_BusMasterEn_OFFSET 2
#define D0F0x04_BusMasterEn_WIDTH 1
#define D0F0x04_BusMasterEn_MASK 0x4
#define D0F0x04_SpecialCycleEn_OFFSET 3
#define D0F0x04_SpecialCycleEn_WIDTH 1
#define D0F0x04_SpecialCycleEn_MASK 0x8
#define D0F0x04_MemWriteInvalidateEn_OFFSET 4
#define D0F0x04_MemWriteInvalidateEn_WIDTH 1
#define D0F0x04_MemWriteInvalidateEn_MASK 0x10
#define D0F0x04_PalSnoopEn_OFFSET 5
#define D0F0x04_PalSnoopEn_WIDTH 1
#define D0F0x04_PalSnoopEn_MASK 0x20
#define D0F0x04_ParityErrorEn_OFFSET 6
#define D0F0x04_ParityErrorEn_WIDTH 1
#define D0F0x04_ParityErrorEn_MASK 0x40
#define D0F0x04_Reserved_7_7_OFFSET 7
#define D0F0x04_Reserved_7_7_WIDTH 1
#define D0F0x04_Reserved_7_7_MASK 0x80
#define D0F0x04_SerrEn_OFFSET 8
#define D0F0x04_SerrEn_WIDTH 1
#define D0F0x04_SerrEn_MASK 0x100
#define D0F0x04_FastB2BEn_OFFSET 9
#define D0F0x04_FastB2BEn_WIDTH 1
#define D0F0x04_FastB2BEn_MASK 0x200
#define D0F0x04_Reserved_19_10_OFFSET 10
#define D0F0x04_Reserved_19_10_WIDTH 10
#define D0F0x04_Reserved_19_10_MASK 0xffc00
#define D0F0x04_CapList_OFFSET 20
#define D0F0x04_CapList_WIDTH 1
#define D0F0x04_CapList_MASK 0x100000
#define D0F0x04_PCI66En_OFFSET 21
#define D0F0x04_PCI66En_WIDTH 1
#define D0F0x04_PCI66En_MASK 0x200000
#define D0F0x04_Reserved_22_22_OFFSET 22
#define D0F0x04_Reserved_22_22_WIDTH 1
#define D0F0x04_Reserved_22_22_MASK 0x400000
#define D0F0x04_FastBackCapable_OFFSET 23
#define D0F0x04_FastBackCapable_WIDTH 1
#define D0F0x04_FastBackCapable_MASK 0x800000
#define D0F0x04_Reserved_24_24_OFFSET 24
#define D0F0x04_Reserved_24_24_WIDTH 1
#define D0F0x04_Reserved_24_24_MASK 0x1000000
#define D0F0x04_DevselTiming_OFFSET 25
#define D0F0x04_DevselTiming_WIDTH 2
#define D0F0x04_DevselTiming_MASK 0x6000000
#define D0F0x04_SignalTargetAbort_OFFSET 27
#define D0F0x04_SignalTargetAbort_WIDTH 1
#define D0F0x04_SignalTargetAbort_MASK 0x8000000
#define D0F0x04_ReceivedTargetAbort_OFFSET 28
#define D0F0x04_ReceivedTargetAbort_WIDTH 1
#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000
#define D0F0x04_ReceivedMasterAbort_OFFSET 29
#define D0F0x04_ReceivedMasterAbort_WIDTH 1
#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000
#define D0F0x04_SignaledSystemError_OFFSET 30
#define D0F0x04_SignaledSystemError_WIDTH 1
#define D0F0x04_SignaledSystemError_MASK 0x40000000
#define D0F0x04_ParityErrorDetected_OFFSET 31
#define D0F0x04_ParityErrorDetected_WIDTH 1
#define D0F0x04_ParityErrorDetected_MASK 0x80000000
/// D0F0x04
typedef union {
struct { ///<
UINT32 IoAccessEn:1 ; ///<
UINT32 MemAccessEn:1 ; ///<
UINT32 BusMasterEn:1 ; ///<
UINT32 SpecialCycleEn:1 ; ///<
UINT32 MemWriteInvalidateEn:1 ; ///<
UINT32 PalSnoopEn:1 ; ///<
UINT32 ParityErrorEn:1 ; ///<
UINT32 Reserved_7_7:1 ; ///<
UINT32 SerrEn:1 ; ///<
UINT32 FastB2BEn:1 ; ///<
UINT32 Reserved_19_10:10; ///<
UINT32 CapList:1 ; ///<
UINT32 PCI66En:1 ; ///<
UINT32 Reserved_22_22:1 ; ///<
UINT32 FastBackCapable:1 ; ///<
UINT32 Reserved_24_24:1 ; ///<
UINT32 DevselTiming:2 ; ///<
UINT32 SignalTargetAbort:1 ; ///<
UINT32 ReceivedTargetAbort:1 ; ///<
UINT32 ReceivedMasterAbort:1 ; ///<
UINT32 SignaledSystemError:1 ; ///<
UINT32 ParityErrorDetected:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x04_STRUCT;
// **** D0F0x08 Register Definition ****
// Address
#define D0F0x08_ADDRESS 0x8
// Type
#define D0F0x08_TYPE TYPE_D0F0
// Field Data
#define D0F0x08_RevID_OFFSET 0
#define D0F0x08_RevID_WIDTH 8
#define D0F0x08_RevID_MASK 0xff
#define D0F0x08_ClassCode_OFFSET 8
#define D0F0x08_ClassCode_WIDTH 24
#define D0F0x08_ClassCode_MASK 0xffffff00
/// D0F0x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x08_STRUCT;
// **** D0F0x0C Register Definition ****
// Address
#define D0F0x0C_ADDRESS 0xc
// Type
#define D0F0x0C_TYPE TYPE_D0F0
// Field Data
#define D0F0x0C_CacheLineSize_OFFSET 0
#define D0F0x0C_CacheLineSize_WIDTH 8
#define D0F0x0C_CacheLineSize_MASK 0xff
#define D0F0x0C_LatencyTimer_OFFSET 8
#define D0F0x0C_LatencyTimer_WIDTH 8
#define D0F0x0C_LatencyTimer_MASK 0xff00
#define D0F0x0C_HeaderTypeReg_OFFSET 16
#define D0F0x0C_HeaderTypeReg_WIDTH 8
#define D0F0x0C_HeaderTypeReg_MASK 0xff0000
#define D0F0x0C_BIST_OFFSET 24
#define D0F0x0C_BIST_WIDTH 8
#define D0F0x0C_BIST_MASK 0xff000000
/// D0F0x0C
typedef union {
struct { ///<
UINT32 CacheLineSize:8 ; ///<
UINT32 LatencyTimer:8 ; ///<
UINT32 HeaderTypeReg:8 ; ///<
UINT32 BIST:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x0C_STRUCT;
// **** D0F0x2C Register Definition ****
// Address
#define D0F0x2C_ADDRESS 0x2c
// Type
#define D0F0x2C_TYPE TYPE_D0F0
// Field Data
#define D0F0x2C_SubsystemVendorID_OFFSET 0
#define D0F0x2C_SubsystemVendorID_WIDTH 16
#define D0F0x2C_SubsystemVendorID_MASK 0xffff
#define D0F0x2C_SubsystemID_OFFSET 16
#define D0F0x2C_SubsystemID_WIDTH 16
#define D0F0x2C_SubsystemID_MASK 0xffff0000
/// D0F0x2C
typedef union {
struct { ///<
UINT32 SubsystemVendorID:16; ///<
UINT32 SubsystemID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x2C_STRUCT;
// **** D0F0x34 Register Definition ****
// Address
#define D0F0x34_ADDRESS 0x34
// Type
#define D0F0x34_TYPE TYPE_D0F0
// Field Data
#define D0F0x34_CapPtr_OFFSET 0
#define D0F0x34_CapPtr_WIDTH 8
#define D0F0x34_CapPtr_MASK 0xff
#define D0F0x34_Reserved_31_8_OFFSET 8
#define D0F0x34_Reserved_31_8_WIDTH 24
#define D0F0x34_Reserved_31_8_MASK 0xffffff00
/// D0F0x34
typedef union {
struct { ///<
UINT32 CapPtr:8 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x34_STRUCT;
// **** D0F0x4C Register Definition ****
// Address
#define D0F0x4C_ADDRESS 0x4c
// Type
#define D0F0x4C_TYPE TYPE_D0F0
// Field Data
#define D0F0x4C_Function1Enable_OFFSET 0
#define D0F0x4C_Function1Enable_WIDTH 1
#define D0F0x4C_Function1Enable_MASK 0x1
#define D0F0x4C_ApicEnable_OFFSET 1
#define D0F0x4C_ApicEnable_WIDTH 1
#define D0F0x4C_ApicEnable_MASK 0x2
#define D0F0x4C_Reserved_2_2_OFFSET 2
#define D0F0x4C_Reserved_2_2_WIDTH 1
#define D0F0x4C_Reserved_2_2_MASK 0x4
#define D0F0x4C_Cf8Dis_OFFSET 3
#define D0F0x4C_Cf8Dis_WIDTH 1
#define D0F0x4C_Cf8Dis_MASK 0x8
#define D0F0x4C_PMEDis_OFFSET 4
#define D0F0x4C_PMEDis_WIDTH 1
#define D0F0x4C_PMEDis_MASK 0x10
#define D0F0x4C_SerrDis_OFFSET 5
#define D0F0x4C_SerrDis_WIDTH 1
#define D0F0x4C_SerrDis_MASK 0x20
#define D0F0x4C_Reserved_10_6_OFFSET 6
#define D0F0x4C_Reserved_10_6_WIDTH 5
#define D0F0x4C_Reserved_10_6_MASK 0x7c0
#define D0F0x4C_CRS_OFFSET 11
#define D0F0x4C_CRS_WIDTH 1
#define D0F0x4C_CRS_MASK 0x800
#define D0F0x4C_CfgRdTime_OFFSET 12
#define D0F0x4C_CfgRdTime_WIDTH 3
#define D0F0x4C_CfgRdTime_MASK 0x7000
#define D0F0x4C_Reserved_22_15_OFFSET 15
#define D0F0x4C_Reserved_22_15_WIDTH 8
#define D0F0x4C_Reserved_22_15_MASK 0x7f8000
#define D0F0x4C_MMIOEnable_OFFSET 23
#define D0F0x4C_MMIOEnable_WIDTH 1
#define D0F0x4C_MMIOEnable_MASK 0x800000
#define D0F0x4C_Reserved_25_24_OFFSET 24
#define D0F0x4C_Reserved_25_24_WIDTH 2
#define D0F0x4C_Reserved_25_24_MASK 0x3000000
#define D0F0x4C_HPDis_OFFSET 26
#define D0F0x4C_HPDis_WIDTH 1
#define D0F0x4C_HPDis_MASK 0x4000000
#define D0F0x4C_Reserved_31_27_OFFSET 27
#define D0F0x4C_Reserved_31_27_WIDTH 5
#define D0F0x4C_Reserved_31_27_MASK 0xf8000000
/// D0F0x4C
typedef union {
struct { ///<
UINT32 Function1Enable:1 ; ///<
UINT32 ApicEnable:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Cf8Dis:1 ; ///<
UINT32 PMEDis:1 ; ///<
UINT32 SerrDis:1 ; ///<
UINT32 Reserved_10_6:5 ; ///<
UINT32 CRS:1 ; ///<
UINT32 CfgRdTime:3 ; ///<
UINT32 Reserved_22_15:8 ; ///<
UINT32 MMIOEnable:1 ; ///<
UINT32 Reserved_25_24:2 ; ///<
UINT32 HPDis:1 ; ///<
UINT32 Reserved_31_27:5 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x4C_STRUCT;
// **** D0F0x60 Register Definition ****
// Address
#define D0F0x60_ADDRESS 0x60
// Type
#define D0F0x60_TYPE TYPE_D0F0
// Field Data
#define D0F0x60_MiscIndAddr_OFFSET 0
#define D0F0x60_MiscIndAddr_WIDTH 7
#define D0F0x60_MiscIndAddr_MASK 0x7f
#define D0F0x60_MiscIndWrEn_OFFSET 7
#define D0F0x60_MiscIndWrEn_WIDTH 1
#define D0F0x60_MiscIndWrEn_MASK 0x80
#define D0F0x60_Reserved_31_8_OFFSET 8
#define D0F0x60_Reserved_31_8_WIDTH 24
#define D0F0x60_Reserved_31_8_MASK 0xffffff00
/// D0F0x60
typedef union {
struct { ///<
UINT32 MiscIndAddr:7 ; ///<
UINT32 MiscIndWrEn:1 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x60_STRUCT;
// **** D0F0x64 Register Definition ****
// Address
#define D0F0x64_ADDRESS 0x64
// Type
#define D0F0x64_TYPE TYPE_D0F0
// Field Data
#define D0F0x64_MiscIndData_OFFSET 0
#define D0F0x64_MiscIndData_WIDTH 32
#define D0F0x64_MiscIndData_MASK 0xffffffff
/// D0F0x64
typedef union {
struct { ///<
UINT32 MiscIndData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x64_STRUCT;
// **** D0F0x7C Register Definition ****
// Address
#define D0F0x7C_ADDRESS 0x7c
// Type
#define D0F0x7C_TYPE TYPE_D0F0
// Field Data
#define D0F0x7C_ForceIntGFXDisable_OFFSET 0
#define D0F0x7C_ForceIntGFXDisable_WIDTH 1
#define D0F0x7C_ForceIntGFXDisable_MASK 0x1
#define D0F0x7C_Reserved_31_1_OFFSET 1
#define D0F0x7C_Reserved_31_1_WIDTH 31
#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe
/// D0F0x7C
typedef union {
struct { ///<
UINT32 ForceIntGFXDisable:1 ; ///<
UINT32 Reserved_31_1:31; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x7C_STRUCT;
// **** D0F0x84 Register Definition ****
// Address
#define D0F0x84_ADDRESS 0x84
// Type
#define D0F0x84_TYPE TYPE_D0F0
// Field Data
#define D0F0x84_Reserved_2_0_OFFSET 0
#define D0F0x84_Reserved_2_0_WIDTH 3
#define D0F0x84_Reserved_2_0_MASK 0x7
#define D0F0x84_VgaHole_OFFSET 3
#define D0F0x84_VgaHole_WIDTH 1
#define D0F0x84_VgaHole_MASK 0x8
#define D0F0x84_Ev6Mode_OFFSET 4
#define D0F0x84_Ev6Mode_WIDTH 1
#define D0F0x84_Ev6Mode_MASK 0x10
#define D0F0x84_Reserved_7_5_OFFSET 5
#define D0F0x84_Reserved_7_5_WIDTH 3
#define D0F0x84_Reserved_7_5_MASK 0xe0
#define D0F0x84_PmeMode_OFFSET 8
#define D0F0x84_PmeMode_WIDTH 1
#define D0F0x84_PmeMode_MASK 0x100
#define D0F0x84_PmeTurnOff_OFFSET 9
#define D0F0x84_PmeTurnOff_WIDTH 1
#define D0F0x84_PmeTurnOff_MASK 0x200
#define D0F0x84_Reserved_31_10_OFFSET 10
#define D0F0x84_Reserved_31_10_WIDTH 22
#define D0F0x84_Reserved_31_10_MASK 0xfffffc00
/// D0F0x84
typedef union {
struct { ///<
UINT32 Reserved_2_0:3 ; ///<
UINT32 VgaHole:1 ; ///<
UINT32 Ev6Mode:1 ; ///<
UINT32 Reserved_7_5:3 ; ///<
UINT32 PmeMode:1 ; ///<
UINT32 PmeTurnOff:1 ; ///<
UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x84_STRUCT;
// **** D0F0x90 Register Definition ****
// Address
#define D0F0x90_ADDRESS 0x90
// Type
#define D0F0x90_TYPE TYPE_D0F0
// Field Data
#define D0F0x90_Reserved_22_0_OFFSET 0
#define D0F0x90_Reserved_22_0_WIDTH 23
#define D0F0x90_Reserved_22_0_MASK 0x7fffff
#define D0F0x90_TopOfDram_OFFSET 23
#define D0F0x90_TopOfDram_WIDTH 9
#define D0F0x90_TopOfDram_MASK 0xff800000
/// D0F0x90
typedef union {
struct { ///<
UINT32 Reserved_22_0:23; ///<
UINT32 TopOfDram:9 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x90_STRUCT;
// **** D0F0x94 Register Definition ****
// Address
#define D0F0x94_ADDRESS 0x94
// Type
#define D0F0x94_TYPE TYPE_D0F0
// Field Data
#define D0F0x94_OrbIndAddr_OFFSET 0
#define D0F0x94_OrbIndAddr_WIDTH 7
#define D0F0x94_OrbIndAddr_MASK 0x7f
#define D0F0x94_Reserved_7_7_OFFSET 7
#define D0F0x94_Reserved_7_7_WIDTH 1
#define D0F0x94_Reserved_7_7_MASK 0x80
#define D0F0x94_OrbIndWrEn_OFFSET 8
#define D0F0x94_OrbIndWrEn_WIDTH 1
#define D0F0x94_OrbIndWrEn_MASK 0x100
#define D0F0x94_Reserved_31_9_OFFSET 9
#define D0F0x94_Reserved_31_9_WIDTH 23
#define D0F0x94_Reserved_31_9_MASK 0xfffffe00
/// D0F0x94
typedef union {
struct { ///<
UINT32 OrbIndAddr:7 ; ///<
UINT32 Reserved_7_7:1 ; ///<
UINT32 OrbIndWrEn:1 ; ///<
UINT32 Reserved_31_9:23; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x94_STRUCT;
// **** D0F0x98 Register Definition ****
// Address
#define D0F0x98_ADDRESS 0x98
// Type
#define D0F0x98_TYPE TYPE_D0F0
// Field Data
#define D0F0x98_OrbIndData_OFFSET 0
#define D0F0x98_OrbIndData_WIDTH 32
#define D0F0x98_OrbIndData_MASK 0xffffffff
/// D0F0x98
typedef union {
struct { ///<
UINT32 OrbIndData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x98_STRUCT;
// **** D0F0xB8 Register Definition ****
// Address
#define D0F0xB8_ADDRESS 0xb8
// Type
#define D0F0xB8_TYPE TYPE_D0F0
// Field Data
#define D0F0xB8_NbSmuIndAddr_OFFSET 0
#define D0F0xB8_NbSmuIndAddr_WIDTH 32
#define D0F0xB8_NbSmuIndAddr_MASK 0xffffffff
/// D0F0xB8
typedef union {
struct { ///<
UINT32 NbSmuIndAddr:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xB8_STRUCT;
// **** D0F0xBC Register Definition ****
// Address
#define D0F0xBC_ADDRESS 0xbc
// Type
#define D0F0xBC_TYPE TYPE_D0F0
// Field Data
#define D0F0xBC_NbSmuIndData_OFFSET 0
#define D0F0xBC_NbSmuIndData_WIDTH 32
#define D0F0xBC_NbSmuIndData_MASK 0xffffffff
/// D0F0xBC
typedef union {
struct { ///<
UINT32 NbSmuIndData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xBC_STRUCT;
// **** D0F0xE0 Register Definition ****
// Address
#define D0F0xE0_ADDRESS 0xe0
// Type
#define D0F0xE0_TYPE TYPE_D0F0
// Field Data
#define D0F0xE0_PcieIndxAddr_OFFSET 0
#define D0F0xE0_PcieIndxAddr_WIDTH 16
#define D0F0xE0_PcieIndxAddr_MASK 0xffff
#define D0F0xE0_FrameType_OFFSET 16
#define D0F0xE0_FrameType_WIDTH 8
#define D0F0xE0_FrameType_MASK 0xff0000
#define D0F0xE0_BlockSelect_OFFSET 24
#define D0F0xE0_BlockSelect_WIDTH 8
#define D0F0xE0_BlockSelect_MASK 0xff000000
/// D0F0xE0
typedef union {
struct { ///<
UINT32 PcieIndxAddr:16; ///<
UINT32 FrameType:8 ; ///<
UINT32 BlockSelect:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE0_STRUCT;
// **** D0F0xE4 Register Definition ****
// Address
#define D0F0xE4_ADDRESS 0xe4
// Type
#define D0F0xE4_TYPE TYPE_D0F0
// Field Data
#define D0F0xE4_PcieIndxData_OFFSET 0
#define D0F0xE4_PcieIndxData_WIDTH 32
#define D0F0xE4_PcieIndxData_MASK 0xffffffff
/// D0F0xE4
typedef union {
struct { ///<
UINT32 PcieIndxData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_STRUCT;
// **** D0F2x00 Register Definition ****
// Address
#define D0F2x00_ADDRESS 0x0
// Type
#define D0F2x00_TYPE TYPE_D0F2
// Field Data
#define D0F2x00_VendorId_OFFSET 0
#define D0F2x00_VendorId_WIDTH 16
#define D0F2x00_VendorId_MASK 0xffff
#define D0F2x00_DeviceId_OFFSET 16
#define D0F2x00_DeviceId_WIDTH 16
#define D0F2x00_DeviceId_MASK 0xffff0000
/// D0F2x00
typedef union {
struct { ///<
UINT32 VendorId:16; ///<
UINT32 DeviceId:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x00_STRUCT;
// **** D0F2x04 Register Definition ****
// Address
#define D0F2x04_ADDRESS 0x4
// Type
#define D0F2x04_TYPE TYPE_D0F2
// Field Data
#define D0F2x04_IoAccessEn_OFFSET 0
#define D0F2x04_IoAccessEn_WIDTH 1
#define D0F2x04_IoAccessEn_MASK 0x1
#define D0F2x04_MemAccessEn_OFFSET 1
#define D0F2x04_MemAccessEn_WIDTH 1
#define D0F2x04_MemAccessEn_MASK 0x2
#define D0F2x04_BusMasterEn_OFFSET 2
#define D0F2x04_BusMasterEn_WIDTH 1
#define D0F2x04_BusMasterEn_MASK 0x4
#define D0F2x04_Reserved_5_3_OFFSET 3
#define D0F2x04_Reserved_5_3_WIDTH 3
#define D0F2x04_Reserved_5_3_MASK 0x38
#define D0F2x04_ParityErrorEn_OFFSET 6
#define D0F2x04_ParityErrorEn_WIDTH 1
#define D0F2x04_ParityErrorEn_MASK 0x40
#define D0F2x04_Reserved_7_7_OFFSET 7
#define D0F2x04_Reserved_7_7_WIDTH 1
#define D0F2x04_Reserved_7_7_MASK 0x80
#define D0F2x04_SerrEn_OFFSET 8
#define D0F2x04_SerrEn_WIDTH 1
#define D0F2x04_SerrEn_MASK 0x100
#define D0F2x04_Reserved_9_9_OFFSET 9
#define D0F2x04_Reserved_9_9_WIDTH 1
#define D0F2x04_Reserved_9_9_MASK 0x200
#define D0F2x04_InterruptDis_OFFSET 10
#define D0F2x04_InterruptDis_WIDTH 1
#define D0F2x04_InterruptDis_MASK 0x400
#define D0F2x04_Reserved_18_11_OFFSET 11
#define D0F2x04_Reserved_18_11_WIDTH 8
#define D0F2x04_Reserved_18_11_MASK 0x7f800
#define D0F2x04_IntStatus_OFFSET 19
#define D0F2x04_IntStatus_WIDTH 1
#define D0F2x04_IntStatus_MASK 0x80000
#define D0F2x04_CapList_OFFSET 20
#define D0F2x04_CapList_WIDTH 1
#define D0F2x04_CapList_MASK 0x100000
#define D0F2x04_Reserved_23_21_OFFSET 21
#define D0F2x04_Reserved_23_21_WIDTH 3
#define D0F2x04_Reserved_23_21_MASK 0xe00000
#define D0F2x04_MasterDataError_OFFSET 24
#define D0F2x04_MasterDataError_WIDTH 1
#define D0F2x04_MasterDataError_MASK 0x1000000
#define D0F2x04_Reserved_26_25_OFFSET 25
#define D0F2x04_Reserved_26_25_WIDTH 2
#define D0F2x04_Reserved_26_25_MASK 0x6000000
#define D0F2x04_SignalTargetAbort_OFFSET 27
#define D0F2x04_SignalTargetAbort_WIDTH 1
#define D0F2x04_SignalTargetAbort_MASK 0x8000000
#define D0F2x04_ReceivedTargetAbort_OFFSET 28
#define D0F2x04_ReceivedTargetAbort_WIDTH 1
#define D0F2x04_ReceivedTargetAbort_MASK 0x10000000
#define D0F2x04_ReceivedMasterAbort_OFFSET 29
#define D0F2x04_ReceivedMasterAbort_WIDTH 1
#define D0F2x04_ReceivedMasterAbort_MASK 0x20000000
#define D0F2x04_SignaledSystemError_OFFSET 30
#define D0F2x04_SignaledSystemError_WIDTH 1
#define D0F2x04_SignaledSystemError_MASK 0x40000000
#define D0F2x04_ParityErrorDetected_OFFSET 31
#define D0F2x04_ParityErrorDetected_WIDTH 1
#define D0F2x04_ParityErrorDetected_MASK 0x80000000
/// D0F2x04
typedef union {
struct { ///<
UINT32 IoAccessEn:1 ; ///<
UINT32 MemAccessEn:1 ; ///<
UINT32 BusMasterEn:1 ; ///<
UINT32 Reserved_5_3:3 ; ///<
UINT32 ParityErrorEn:1 ; ///<
UINT32 Reserved_7_7:1 ; ///<
UINT32 SerrEn:1 ; ///<
UINT32 Reserved_9_9:1 ; ///<
UINT32 InterruptDis:1 ; ///<
UINT32 Reserved_18_11:8 ; ///<
UINT32 IntStatus:1 ; ///<
UINT32 CapList:1 ; ///<
UINT32 Reserved_23_21:3 ; ///<
UINT32 MasterDataError:1 ; ///<
UINT32 Reserved_26_25:2 ; ///<
UINT32 SignalTargetAbort:1 ; ///<
UINT32 ReceivedTargetAbort:1 ; ///<
UINT32 ReceivedMasterAbort:1 ; ///<
UINT32 SignaledSystemError:1 ; ///<
UINT32 ParityErrorDetected:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x04_STRUCT;
// **** D0F2x08 Register Definition ****
// Address
#define D0F2x08_ADDRESS 0x8
// Type
#define D0F2x08_TYPE TYPE_D0F2
// Field Data
#define D0F2x08_RevID_OFFSET 0
#define D0F2x08_RevID_WIDTH 8
#define D0F2x08_RevID_MASK 0xff
#define D0F2x08_ClassCode_OFFSET 8
#define D0F2x08_ClassCode_WIDTH 24
#define D0F2x08_ClassCode_MASK 0xffffff00
/// D0F2x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x08_STRUCT;
// **** D0F2x0C Register Definition ****
// Address
#define D0F2x0C_ADDRESS 0xc
// Type
#define D0F2x0C_TYPE TYPE_D0F2
// Field Data
#define D0F2x0C_CacheLineSize_OFFSET 0
#define D0F2x0C_CacheLineSize_WIDTH 8
#define D0F2x0C_CacheLineSize_MASK 0xff
#define D0F2x0C_LatencyTimer_OFFSET 8
#define D0F2x0C_LatencyTimer_WIDTH 8
#define D0F2x0C_LatencyTimer_MASK 0xff00
#define D0F2x0C_HeaderTypeReg_OFFSET 16
#define D0F2x0C_HeaderTypeReg_WIDTH 8
#define D0F2x0C_HeaderTypeReg_MASK 0xff0000
#define D0F2x0C_BIST_OFFSET 24
#define D0F2x0C_BIST_WIDTH 8
#define D0F2x0C_BIST_MASK 0xff000000
/// D0F2x0C
typedef union {
struct { ///<
UINT32 CacheLineSize:8 ; ///<
UINT32 LatencyTimer:8 ; ///<
UINT32 HeaderTypeReg:8 ; ///<
UINT32 BIST:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x0C_STRUCT;
// **** D0F2x2C Register Definition ****
// Address
#define D0F2x2C_ADDRESS 0x2c
// Type
#define D0F2x2C_TYPE TYPE_D0F2
// Field Data
#define D0F2x2C_SubsystemVendorId_OFFSET 0
#define D0F2x2C_SubsystemVendorId_WIDTH 16
#define D0F2x2C_SubsystemVendorId_MASK 0xffff
#define D0F2x2C_SubsystemId_OFFSET 16
#define D0F2x2C_SubsystemId_WIDTH 16
#define D0F2x2C_SubsystemId_MASK 0xffff0000
/// D0F2x2C
typedef union {
struct { ///<
UINT32 SubsystemVendorId:16; ///<
UINT32 SubsystemId:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x2C_STRUCT;
// **** D0F2x34 Register Definition ****
// Address
#define D0F2x34_ADDRESS 0x34
// Type
#define D0F2x34_TYPE TYPE_D0F2
// Field Data
#define D0F2x34_CapPtr_OFFSET 0
#define D0F2x34_CapPtr_WIDTH 8
#define D0F2x34_CapPtr_MASK 0xff
#define D0F2x34_Reserved_31_8_OFFSET 8
#define D0F2x34_Reserved_31_8_WIDTH 24
#define D0F2x34_Reserved_31_8_MASK 0xffffff00
/// D0F2x34
typedef union {
struct { ///<
UINT32 CapPtr:8 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x34_STRUCT;
// **** D0F2x3C Register Definition ****
// Address
#define D0F2x3C_ADDRESS 0x3c
// Type
#define D0F2x3C_TYPE TYPE_D0F2
// Field Data
#define D0F2x3C_InterruptLine_OFFSET 0
#define D0F2x3C_InterruptLine_WIDTH 8
#define D0F2x3C_InterruptLine_MASK 0xff
#define D0F2x3C_InterruptPin_OFFSET 8
#define D0F2x3C_InterruptPin_WIDTH 8
#define D0F2x3C_InterruptPin_MASK 0xff00
#define D0F2x3C_Reserved_31_16_OFFSET 16
#define D0F2x3C_Reserved_31_16_WIDTH 16
#define D0F2x3C_Reserved_31_16_MASK 0xffff0000
/// D0F2x3C
typedef union {
struct { ///<
UINT32 InterruptLine:8 ; ///<
UINT32 InterruptPin:8 ; ///<
UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x3C_STRUCT;
// **** D0F2x40 Register Definition ****
// Address
#define D0F2x40_ADDRESS 0x40
// Type
#define D0F2x40_TYPE TYPE_D0F2
// Field Data
#define D0F2x40_IommuCapId_OFFSET 0
#define D0F2x40_IommuCapId_WIDTH 8
#define D0F2x40_IommuCapId_MASK 0xff
#define D0F2x40_IommuCapPtr_OFFSET 8
#define D0F2x40_IommuCapPtr_WIDTH 8
#define D0F2x40_IommuCapPtr_MASK 0xff00
#define D0F2x40_IommuCapType_OFFSET 16
#define D0F2x40_IommuCapType_WIDTH 3
#define D0F2x40_IommuCapType_MASK 0x70000
#define D0F2x40_IommuCapRev_OFFSET 19
#define D0F2x40_IommuCapRev_WIDTH 5
#define D0F2x40_IommuCapRev_MASK 0xf80000
#define D0F2x40_IommuIoTlbsup_OFFSET 24
#define D0F2x40_IommuIoTlbsup_WIDTH 1
#define D0F2x40_IommuIoTlbsup_MASK 0x1000000
#define D0F2x40_IommuHtTunnelSup_OFFSET 25
#define D0F2x40_IommuHtTunnelSup_WIDTH 1
#define D0F2x40_IommuHtTunnelSup_MASK 0x2000000
#define D0F2x40_IommuNpCache_OFFSET 26
#define D0F2x40_IommuNpCache_WIDTH 1
#define D0F2x40_IommuNpCache_MASK 0x4000000
#define D0F2x40_IommuEfrSup_OFFSET 27
#define D0F2x40_IommuEfrSup_WIDTH 1
#define D0F2x40_IommuEfrSup_MASK 0x8000000
#define D0F2x40_Reserved_31_28_OFFSET 28
#define D0F2x40_Reserved_31_28_WIDTH 4
#define D0F2x40_Reserved_31_28_MASK 0xf0000000
/// D0F2x40
typedef union {
struct { ///<
UINT32 IommuCapId:8 ; ///<
UINT32 IommuCapPtr:8 ; ///<
UINT32 IommuCapType:3 ; ///<
UINT32 IommuCapRev:5 ; ///<
UINT32 IommuIoTlbsup:1 ; ///<
UINT32 IommuHtTunnelSup:1 ; ///<
UINT32 IommuNpCache:1 ; ///<
UINT32 IommuEfrSup:1 ; ///<
UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x40_STRUCT;
// **** D0F2x44 Register Definition ****
// Address
#define D0F2x44_ADDRESS 0x44
// Type
#define D0F2x44_TYPE TYPE_D0F2
// Field Data
#define D0F2x44_IommuEnable_OFFSET 0
#define D0F2x44_IommuEnable_WIDTH 1
#define D0F2x44_IommuEnable_MASK 0x1
#define D0F2x44_Reserved_13_1_OFFSET 1
#define D0F2x44_Reserved_13_1_WIDTH 13
#define D0F2x44_Reserved_13_1_MASK 0x3ffe
#define D0F2x44_IommuBaseAddr_31_14__OFFSET 14
#define D0F2x44_IommuBaseAddr_31_14__WIDTH 18
#define D0F2x44_IommuBaseAddr_31_14__MASK 0xffffc000
/// D0F2x44
typedef union {
struct { ///<
UINT32 IommuEnable:1 ; ///<
UINT32 Reserved_13_1:13; ///<
UINT32 IommuBaseAddr_31_14_:18; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x44_STRUCT;
// **** D0F2x48 Register Definition ****
// Address
#define D0F2x48_ADDRESS 0x48
// Type
#define D0F2x48_TYPE TYPE_D0F2
// Field Data
#define D0F2x48_IommuBaseAddr_63_32__OFFSET 0
#define D0F2x48_IommuBaseAddr_63_32__WIDTH 32
#define D0F2x48_IommuBaseAddr_63_32__MASK 0xffffffff
/// D0F2x48
typedef union {
struct { ///<
UINT32 IommuBaseAddr_63_32_:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x48_STRUCT;
// **** D0F2x4C Register Definition ****
// Address
#define D0F2x4C_ADDRESS 0x4c
// Type
#define D0F2x4C_TYPE TYPE_D0F2
// Field Data
#define D0F2x4C_IommuUnitId_OFFSET 0
#define D0F2x4C_IommuUnitId_WIDTH 5
#define D0F2x4C_IommuUnitId_MASK 0x1f
#define D0F2x4C_Reserved_6_5_OFFSET 5
#define D0F2x4C_Reserved_6_5_WIDTH 2
#define D0F2x4C_Reserved_6_5_MASK 0x60
#define D0F2x4C_IommuRngValid_OFFSET 7
#define D0F2x4C_IommuRngValid_WIDTH 1
#define D0F2x4C_IommuRngValid_MASK 0x80
#define D0F2x4C_IommuBusNumber_OFFSET 8
#define D0F2x4C_IommuBusNumber_WIDTH 8
#define D0F2x4C_IommuBusNumber_MASK 0xff00
#define D0F2x4C_IommuFirstDevice_OFFSET 16
#define D0F2x4C_IommuFirstDevice_WIDTH 8
#define D0F2x4C_IommuFirstDevice_MASK 0xff0000
#define D0F2x4C_IommuLastDevice_OFFSET 24
#define D0F2x4C_IommuLastDevice_WIDTH 8
#define D0F2x4C_IommuLastDevice_MASK 0xff000000
/// D0F2x4C
typedef union {
struct { ///<
UINT32 IommuUnitId:5 ; ///<
UINT32 Reserved_6_5:2 ; ///<
UINT32 IommuRngValid:1 ; ///<
UINT32 IommuBusNumber:8 ; ///<
UINT32 IommuFirstDevice:8 ; ///<
UINT32 IommuLastDevice:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x4C_STRUCT;
// **** D0F2x50 Register Definition ****
// Address
#define D0F2x50_ADDRESS 0x50
// Type
#define D0F2x50_TYPE TYPE_D0F2
// Field Data
#define D0F2x50_IommuMsiNum_OFFSET 0
#define D0F2x50_IommuMsiNum_WIDTH 5
#define D0F2x50_IommuMsiNum_MASK 0x1f
#define D0F2x50_IommuGvaSize_OFFSET 5
#define D0F2x50_IommuGvaSize_WIDTH 3
#define D0F2x50_IommuGvaSize_MASK 0xe0
#define D0F2x50_IommuPaSize_OFFSET 8
#define D0F2x50_IommuPaSize_WIDTH 7
#define D0F2x50_IommuPaSize_MASK 0x7f00
#define D0F2x50_IommuVaSize_OFFSET 15
#define D0F2x50_IommuVaSize_WIDTH 7
#define D0F2x50_IommuVaSize_MASK 0x3f8000
#define D0F2x50_IommuHtAtsResv_OFFSET 22
#define D0F2x50_IommuHtAtsResv_WIDTH 1
#define D0F2x50_IommuHtAtsResv_MASK 0x400000
#define D0F2x50_Reserved_26_23_OFFSET 23
#define D0F2x50_Reserved_26_23_WIDTH 4
#define D0F2x50_Reserved_26_23_MASK 0x7800000
#define D0F2x50_IommuMsiNumPpr_OFFSET 27
#define D0F2x50_IommuMsiNumPpr_WIDTH 5
#define D0F2x50_IommuMsiNumPpr_MASK 0xf8000000
/// D0F2x50
typedef union {
struct { ///<
UINT32 IommuMsiNum:5 ; ///<
UINT32 IommuGvaSize:3 ; ///<
UINT32 IommuPaSize:7 ; ///<
UINT32 IommuVaSize:7 ; ///<
UINT32 IommuHtAtsResv:1 ; ///<
UINT32 Reserved_26_23:4 ; ///<
UINT32 IommuMsiNumPpr:5 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x50_STRUCT;
// **** D0F2x54 Register Definition ****
// Address
#define D0F2x54_ADDRESS 0x54
// Type
#define D0F2x54_TYPE TYPE_D0F2
// Field Data
#define D0F2x54_MsiCapId_OFFSET 0
#define D0F2x54_MsiCapId_WIDTH 8
#define D0F2x54_MsiCapId_MASK 0xff
#define D0F2x54_MsiCapPtr_OFFSET 8
#define D0F2x54_MsiCapPtr_WIDTH 8
#define D0F2x54_MsiCapPtr_MASK 0xff00
#define D0F2x54_MsiEn_OFFSET 16
#define D0F2x54_MsiEn_WIDTH 1
#define D0F2x54_MsiEn_MASK 0x10000
#define D0F2x54_MsiMultMessCap_OFFSET 17
#define D0F2x54_MsiMultMessCap_WIDTH 3
#define D0F2x54_MsiMultMessCap_MASK 0xe0000
#define D0F2x54_MsiMultMessEn_OFFSET 20
#define D0F2x54_MsiMultMessEn_WIDTH 3
#define D0F2x54_MsiMultMessEn_MASK 0x700000
#define D0F2x54_Msi64En_OFFSET 23
#define D0F2x54_Msi64En_WIDTH 1
#define D0F2x54_Msi64En_MASK 0x800000
#define D0F2x54_Reserved_31_24_OFFSET 24
#define D0F2x54_Reserved_31_24_WIDTH 8
#define D0F2x54_Reserved_31_24_MASK 0xff000000
/// D0F2x54
typedef union {
struct { ///<
UINT32 MsiCapId:8 ; ///<
UINT32 MsiCapPtr:8 ; ///<
UINT32 MsiEn:1 ; ///<
UINT32 MsiMultMessCap:3 ; ///<
UINT32 MsiMultMessEn:3 ; ///<
UINT32 Msi64En:1 ; ///<
UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x54_STRUCT;
// **** D0F2x58 Register Definition ****
// Address
#define D0F2x58_ADDRESS 0x58
// Type
#define D0F2x58_TYPE TYPE_D0F2
// Field Data
#define D0F2x58_Reserved_1_0_OFFSET 0
#define D0F2x58_Reserved_1_0_WIDTH 2
#define D0F2x58_Reserved_1_0_MASK 0x3
#define D0F2x58_MsiAddr_31_2__OFFSET 2
#define D0F2x58_MsiAddr_31_2__WIDTH 30
#define D0F2x58_MsiAddr_31_2__MASK 0xfffffffc
/// D0F2x58
typedef union {
struct { ///<
UINT32 Reserved_1_0:2 ; ///<
UINT32 MsiAddr_31_2_:30; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x58_STRUCT;
// **** D0F2x5C Register Definition ****
// Address
#define D0F2x5C_ADDRESS 0x5c
// Type
#define D0F2x5C_TYPE TYPE_D0F2
// Field Data
#define D0F2x5C_MsiAddr_63_32__OFFSET 0
#define D0F2x5C_MsiAddr_63_32__WIDTH 32
#define D0F2x5C_MsiAddr_63_32__MASK 0xffffffff
/// D0F2x5C
typedef union {
struct { ///<
UINT32 MsiAddr_63_32_:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x5C_STRUCT;
// **** D0F2x60 Register Definition ****
// Address
#define D0F2x60_ADDRESS 0x60
// Type
#define D0F2x60_TYPE TYPE_D0F2
// Field Data
#define D0F2x60_MsiData_OFFSET 0
#define D0F2x60_MsiData_WIDTH 16
#define D0F2x60_MsiData_MASK 0xffff
#define D0F2x60_Reserved_31_16_OFFSET 16
#define D0F2x60_Reserved_31_16_WIDTH 16
#define D0F2x60_Reserved_31_16_MASK 0xffff0000
/// D0F2x60
typedef union {
struct { ///<
UINT32 MsiData:16; ///<
UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x60_STRUCT;
// **** D0F2x64 Register Definition ****
// Address
#define D0F2x64_ADDRESS 0x64
// Type
#define D0F2x64_TYPE TYPE_D0F2
// Field Data
#define D0F2x64_MsiMapCapId_OFFSET 0
#define D0F2x64_MsiMapCapId_WIDTH 8
#define D0F2x64_MsiMapCapId_MASK 0xff
#define D0F2x64_MsiMapCapPtr_OFFSET 8
#define D0F2x64_MsiMapCapPtr_WIDTH 8
#define D0F2x64_MsiMapCapPtr_MASK 0xff00
#define D0F2x64_MsiMapEn_OFFSET 16
#define D0F2x64_MsiMapEn_WIDTH 1
#define D0F2x64_MsiMapEn_MASK 0x10000
#define D0F2x64_MsiMapFixd_OFFSET 17
#define D0F2x64_MsiMapFixd_WIDTH 1
#define D0F2x64_MsiMapFixd_MASK 0x20000
#define D0F2x64_Reserved_26_18_OFFSET 18
#define D0F2x64_Reserved_26_18_WIDTH 9
#define D0F2x64_Reserved_26_18_MASK 0x7fc0000
#define D0F2x64_MsiMapCapType_OFFSET 27
#define D0F2x64_MsiMapCapType_WIDTH 5
#define D0F2x64_MsiMapCapType_MASK 0xf8000000
/// D0F2x64
typedef union {
struct { ///<
UINT32 MsiMapCapId:8 ; ///<
UINT32 MsiMapCapPtr:8 ; ///<
UINT32 MsiMapEn:1 ; ///<
UINT32 MsiMapFixd:1 ; ///<
UINT32 Reserved_26_18:9 ; ///<
UINT32 MsiMapCapType:5 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x64_STRUCT;
// **** D0F2x6C Register Definition ****
// Address
#define D0F2x6C_ADDRESS 0x6c
// Type
#define D0F2x6C_TYPE TYPE_D0F2
// Field Data
#define D0F2x6C_InterruptPinW_OFFSET 0
#define D0F2x6C_InterruptPinW_WIDTH 3
#define D0F2x6C_InterruptPinW_MASK 0x7
#define D0F2x6C_Reserved_3_3_OFFSET 3
#define D0F2x6C_Reserved_3_3_WIDTH 1
#define D0F2x6C_Reserved_3_3_MASK 0x8
#define D0F2x6C_MinorRevIdW_OFFSET 4
#define D0F2x6C_MinorRevIdW_WIDTH 4
#define D0F2x6C_MinorRevIdW_MASK 0xf0
#define D0F2x6C_IoTlbsupW_OFFSET 8
#define D0F2x6C_IoTlbsupW_WIDTH 1
#define D0F2x6C_IoTlbsupW_MASK 0x100
#define D0F2x6C_EfrSupW_OFFSET 9
#define D0F2x6C_EfrSupW_WIDTH 1
#define D0F2x6C_EfrSupW_MASK 0x200
#define D0F2x6C_Reserved_31_10_OFFSET 10
#define D0F2x6C_Reserved_31_10_WIDTH 22
#define D0F2x6C_Reserved_31_10_MASK 0xfffffc00
/// D0F2x6C
typedef union {
struct { ///<
UINT32 InterruptPinW:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 MinorRevIdW:4 ; ///<
UINT32 IoTlbsupW:1 ; ///<
UINT32 EfrSupW:1 ; ///<
UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x6C_STRUCT;
// **** D0F2x70 Register Definition ****
// Address
#define D0F2x70_ADDRESS 0x70
// Type
#define D0F2x70_TYPE TYPE_D0F2
// Field Data
#define D0F2x70_PrefSupW_OFFSET 0
#define D0F2x70_PrefSupW_WIDTH 1
#define D0F2x70_PrefSupW_MASK 0x1
#define D0F2x70_PprSupW_OFFSET 1
#define D0F2x70_PprSupW_WIDTH 1
#define D0F2x70_PprSupW_MASK 0x2
#define D0F2x70_Reserved_2_2_OFFSET 2
#define D0F2x70_Reserved_2_2_WIDTH 1
#define D0F2x70_Reserved_2_2_MASK 0x4
#define D0F2x70_NxSupW_OFFSET 3
#define D0F2x70_NxSupW_WIDTH 1
#define D0F2x70_NxSupW_MASK 0x8
#define D0F2x70_GtSupW_OFFSET 4
#define D0F2x70_GtSupW_WIDTH 1
#define D0F2x70_GtSupW_MASK 0x10
#define D0F2x70_Reserved_5_5_OFFSET 5
#define D0F2x70_Reserved_5_5_WIDTH 1
#define D0F2x70_Reserved_5_5_MASK 0x20
#define D0F2x70_IaSupW_OFFSET 6
#define D0F2x70_IaSupW_WIDTH 1
#define D0F2x70_IaSupW_MASK 0x40
#define D0F2x70_Reserved_7_7_OFFSET 7
#define D0F2x70_Reserved_7_7_WIDTH 1
#define D0F2x70_Reserved_7_7_MASK 0x80
#define D0F2x70_Reserved_8_8_OFFSET 8
#define D0F2x70_Reserved_8_8_WIDTH 1
#define D0F2x70_Reserved_8_8_MASK 0x100
#define D0F2x70_PcSupW_OFFSET 9
#define D0F2x70_PcSupW_WIDTH 1
#define D0F2x70_PcSupW_MASK 0x200
#define D0F2x70_HatsW_OFFSET 10
#define D0F2x70_HatsW_WIDTH 2
#define D0F2x70_HatsW_MASK 0xc00
#define D0F2x70_Reserved_31_12_OFFSET 12
#define D0F2x70_Reserved_31_12_WIDTH 20
#define D0F2x70_Reserved_31_12_MASK 0xfffff000
/// D0F2x70
typedef union {
struct { ///<
UINT32 PrefSupW:1 ; ///<
UINT32 PprSupW:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 NxSupW:1 ; ///<
UINT32 GtSupW:1 ; ///<
UINT32 Reserved_5_5:1 ; ///<
UINT32 IaSupW:1 ; ///<
UINT32 Reserved_7_7:1 ; ///<
UINT32 Reserved_8_8:1 ; ///<
UINT32 PcSupW:1 ; ///<
UINT32 HatsW:2 ; ///<
UINT32 Reserved_31_12:20; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x70_STRUCT;
// **** D0F2x74 Register Definition ****
// Address
#define D0F2x74_ADDRESS 0x74
// Type
#define D0F2x74_TYPE TYPE_D0F2
// Field Data
#define D0F2x74_PasMaxW_OFFSET 0
#define D0F2x74_PasMaxW_WIDTH 4
#define D0F2x74_PasMaxW_MASK 0xf
#define D0F2x74_Reserved_31_4_OFFSET 4
#define D0F2x74_Reserved_31_4_WIDTH 28
#define D0F2x74_Reserved_31_4_MASK 0xfffffff0
/// D0F2x74
typedef union {
struct { ///<
UINT32 PasMaxW:4 ; ///<
UINT32 Reserved_31_4:28; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x74_STRUCT;
// **** D0F2x78 Register Definition ****
// Address
#define D0F2x78_ADDRESS 0x78
// Type
#define D0F2x78_TYPE TYPE_D0F2
// Field Data
#define D0F2x78_Reserved_6_0_OFFSET 0
#define D0F2x78_Reserved_6_0_WIDTH 7
#define D0F2x78_Reserved_6_0_MASK 0x7f
#define D0F2x78_RngValidW_OFFSET 7
#define D0F2x78_RngValidW_WIDTH 1
#define D0F2x78_RngValidW_MASK 0x80
#define D0F2x78_BusNumberW_OFFSET 8
#define D0F2x78_BusNumberW_WIDTH 8
#define D0F2x78_BusNumberW_MASK 0xff00
#define D0F2x78_FirstDeviceW_OFFSET 16
#define D0F2x78_FirstDeviceW_WIDTH 8
#define D0F2x78_FirstDeviceW_MASK 0xff0000
#define D0F2x78_LastDeviceW_OFFSET 24
#define D0F2x78_LastDeviceW_WIDTH 8
#define D0F2x78_LastDeviceW_MASK 0xff000000
/// D0F2x78
typedef union {
struct { ///<
UINT32 Reserved_6_0:7 ; ///<
UINT32 RngValidW:1 ; ///<
UINT32 BusNumberW:8 ; ///<
UINT32 FirstDeviceW:8 ; ///<
UINT32 LastDeviceW:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2x78_STRUCT;
// **** D0F2xF0 Register Definition ****
// Address
#define D0F2xF0_ADDRESS 0xf0
// Type
#define D0F2xF0_TYPE TYPE_D0F2
// Field Data
#define D0F2xF0_L2cfgIndex_OFFSET 0
#define D0F2xF0_L2cfgIndex_WIDTH 8
#define D0F2xF0_L2cfgIndex_MASK 0xff
#define D0F2xF0_L2cfgWrEn_OFFSET 8
#define D0F2xF0_L2cfgWrEn_WIDTH 1
#define D0F2xF0_L2cfgWrEn_MASK 0x100
#define D0F2xF0_Reserved_31_9_OFFSET 9
#define D0F2xF0_Reserved_31_9_WIDTH 23
#define D0F2xF0_Reserved_31_9_MASK 0xfffffe00
/// D0F2xF0
typedef union {
struct { ///<
UINT32 L2cfgIndex:8 ; ///<
UINT32 L2cfgWrEn:1 ; ///<
UINT32 Reserved_31_9:23; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2xF0_STRUCT;
// **** D0F2xF4 Register Definition ****
// Address
#define D0F2xF4_ADDRESS 0xf4
// Type
#define D0F2xF4_TYPE TYPE_D0F2
// Field Data
#define D0F2xF4_L2cfgData_OFFSET 0
#define D0F2xF4_L2cfgData_WIDTH 32
#define D0F2xF4_L2cfgData_MASK 0xffffffff
/// D0F2xF4
typedef union {
struct { ///<
UINT32 L2cfgData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2xF4_STRUCT;
// **** D0F2xF8 Register Definition ****
// Address
#define D0F2xF8_ADDRESS 0xf8
// Type
#define D0F2xF8_TYPE TYPE_D0F2
// Field Data
#define D0F2xF8_L1cfgIndex_OFFSET 0
#define D0F2xF8_L1cfgIndex_WIDTH 16
#define D0F2xF8_L1cfgIndex_MASK 0xffff
#define D0F2xF8_L1cfgSel_OFFSET 16
#define D0F2xF8_L1cfgSel_WIDTH 4
#define D0F2xF8_L1cfgSel_MASK 0xf0000
#define D0F2xF8_Reserved_30_20_OFFSET 20
#define D0F2xF8_Reserved_30_20_WIDTH 11
#define D0F2xF8_Reserved_30_20_MASK 0x7ff00000
#define D0F2xF8_L1cfgEn_OFFSET 31
#define D0F2xF8_L1cfgEn_WIDTH 1
#define D0F2xF8_L1cfgEn_MASK 0x80000000
/// D0F2xF8
typedef union {
struct { ///<
UINT32 L1cfgIndex:16; ///<
UINT32 L1cfgSel:4 ; ///<
UINT32 Reserved_30_20:11; ///<
UINT32 L1cfgEn:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2xF8_STRUCT;
// **** D0F2xFC Register Definition ****
// Address
#define D0F2xFC_ADDRESS 0xfc
// Type
#define D0F2xFC_TYPE TYPE_D0F2
// Field Data
#define D0F2xFC_L1cfgData_OFFSET 0
#define D0F2xFC_L1cfgData_WIDTH 32
#define D0F2xFC_L1cfgData_MASK 0xffffffff
/// D0F2xFC
typedef union {
struct { ///<
UINT32 L1cfgData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F2xFC_STRUCT;
// **** D18F0x00 Register Definition ****
// Address
#define D18F0x00_ADDRESS 0x0
// Type
#define D18F0x00_TYPE TYPE_D18F0
// Field Data
#define D18F0x00_VendorID_OFFSET 0
#define D18F0x00_VendorID_WIDTH 16
#define D18F0x00_VendorID_MASK 0xffff
#define D18F0x00_DeviceID_OFFSET 16
#define D18F0x00_DeviceID_WIDTH 16
#define D18F0x00_DeviceID_MASK 0xffff0000
/// D18F0x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x00_STRUCT;
// **** D18F0x04 Register Definition ****
// Address
#define D18F0x04_ADDRESS 0x4
// Type
#define D18F0x04_TYPE TYPE_D18F0
// Field Data
#define D18F0x04_Command_OFFSET 0
#define D18F0x04_Command_WIDTH 16
#define D18F0x04_Command_MASK 0xffff
#define D18F0x04_Status_OFFSET 16
#define D18F0x04_Status_WIDTH 16
#define D18F0x04_Status_MASK 0xffff0000
/// D18F0x04
typedef union {
struct { ///<
UINT32 Command:16; ///<
UINT32 Status:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x04_STRUCT;
// **** D18F0x08 Register Definition ****
// Address
#define D18F0x08_ADDRESS 0x8
// Type
#define D18F0x08_TYPE TYPE_D18F0
// Field Data
#define D18F0x08_RevID_OFFSET 0
#define D18F0x08_RevID_WIDTH 8
#define D18F0x08_RevID_MASK 0xff
#define D18F0x08_ClassCode_OFFSET 8
#define D18F0x08_ClassCode_WIDTH 24
#define D18F0x08_ClassCode_MASK 0xffffff00
/// D18F0x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x08_STRUCT;
// **** D18F0x0C Register Definition ****
// Address
#define D18F0x0C_ADDRESS 0xc
// Type
#define D18F0x0C_TYPE TYPE_D18F0
// Field Data
#define D18F0x0C_HeaderTypeReg_OFFSET 0
#define D18F0x0C_HeaderTypeReg_WIDTH 32
#define D18F0x0C_HeaderTypeReg_MASK 0xffffffff
/// D18F0x0C
typedef union {
struct { ///<
UINT32 HeaderTypeReg:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x0C_STRUCT;
// **** D18F0x34 Register Definition ****
// Address
#define D18F0x34_ADDRESS 0x34
// Type
#define D18F0x34_TYPE TYPE_D18F0
// Field Data
#define D18F0x34_CapPtr_OFFSET 0
#define D18F0x34_CapPtr_WIDTH 8
#define D18F0x34_CapPtr_MASK 0xff
#define D18F0x34_Reserved_31_8_OFFSET 8
#define D18F0x34_Reserved_31_8_WIDTH 24
#define D18F0x34_Reserved_31_8_MASK 0xffffff00
/// D18F0x34
typedef union {
struct { ///<
UINT32 CapPtr:8 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x34_STRUCT;
// **** D18F0x40 Register Definition ****
// Address
#define D18F0x40_ADDRESS 0x40
// Type
#define D18F0x40_TYPE TYPE_D18F0
// Field Data
#define D18F0x40_Reserved_31_0_OFFSET 0
#define D18F0x40_Reserved_31_0_WIDTH 32
#define D18F0x40_Reserved_31_0_MASK 0xffffffff
/// D18F0x40
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x40_STRUCT;
// **** D18F0x60 Register Definition ****
// Address
#define D18F0x60_ADDRESS 0x60
// Type
#define D18F0x60_TYPE TYPE_D18F0
// Field Data
#define D18F0x60_Reserved_15_0_OFFSET 0
#define D18F0x60_Reserved_15_0_WIDTH 16
#define D18F0x60_Reserved_15_0_MASK 0xffff
#define D18F0x60_CpuCnt_4_0__OFFSET 16
#define D18F0x60_CpuCnt_4_0__WIDTH 5
#define D18F0x60_CpuCnt_4_0__MASK 0x1f0000
#define D18F0x60_Reserved_31_21_OFFSET 21
#define D18F0x60_Reserved_31_21_WIDTH 11
#define D18F0x60_Reserved_31_21_MASK 0xffe00000
/// D18F0x60
typedef union {
struct { ///<
UINT32 Reserved_15_0:16; ///<
UINT32 CpuCnt_4_0_:5 ; ///<
UINT32 Reserved_31_21:11; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x60_STRUCT;
// **** D18F0x64 Register Definition ****
// Address
#define D18F0x64_ADDRESS 0x64
// Type
#define D18F0x64_TYPE TYPE_D18F0
// Field Data
#define D18F0x64_MctUnit_OFFSET 4
#define D18F0x64_MctUnit_WIDTH 2
#define D18F0x64_MctUnit_MASK 0x30
#define D18F0x64_HbUnit_OFFSET 6
#define D18F0x64_HbUnit_WIDTH 2
#define D18F0x64_HbUnit_MASK 0xc0
#define D18F0x64_Reserved_31_8_OFFSET 8
#define D18F0x64_Reserved_31_8_WIDTH 24
#define D18F0x64_Reserved_31_8_MASK 0xffffff00
/// D18F0x64
typedef union {
struct { ///<
UINT32 CpuUnit:2 ; ///<
UINT32 ExtCpuUnit:2 ; ///<
UINT32 MctUnit:2 ; ///<
UINT32 HbUnit:2 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x64_STRUCT;
// **** D18F0x68 Register Definition ****
// Address
#define D18F0x68_ADDRESS 0x68
// Type
#define D18F0x68_TYPE TYPE_D18F0
// Field Data
#define D18F0x68_Reserved_3_0_OFFSET 0
#define D18F0x68_Reserved_3_0_WIDTH 4
#define D18F0x68_Reserved_3_0_MASK 0xf
#define D18F0x68_DisMTS_OFFSET 4
#define D18F0x68_DisMTS_WIDTH 1
#define D18F0x68_DisMTS_MASK 0x10
#define D18F0x68_Reserved_5_5_OFFSET 5
#define D18F0x68_Reserved_5_5_WIDTH 1
#define D18F0x68_Reserved_5_5_MASK 0x20
#define D18F0x68_CPUReqPassPW_OFFSET 6
#define D18F0x68_CPUReqPassPW_WIDTH 1
#define D18F0x68_CPUReqPassPW_MASK 0x40
#define D18F0x68_CPURdRspPassPW_OFFSET 7
#define D18F0x68_CPURdRspPassPW_WIDTH 1
#define D18F0x68_CPURdRspPassPW_MASK 0x80
#define D18F0x68_DisPMemC_OFFSET 8
#define D18F0x68_DisPMemC_WIDTH 1
#define D18F0x68_DisPMemC_MASK 0x100
#define D18F0x68_DisRmtPMemC_OFFSET 9
#define D18F0x68_DisRmtPMemC_WIDTH 1
#define D18F0x68_DisRmtPMemC_MASK 0x200
#define D18F0x68_DisFillP_OFFSET 10
#define D18F0x68_DisFillP_WIDTH 1
#define D18F0x68_DisFillP_MASK 0x400
#define D18F0x68_RespPassPW_OFFSET 11
#define D18F0x68_RespPassPW_WIDTH 1
#define D18F0x68_RespPassPW_MASK 0x800
#define D18F0x68_Reserved_14_12_OFFSET 12
#define D18F0x68_Reserved_14_12_WIDTH 3
#define D18F0x68_Reserved_14_12_MASK 0x7000
#define D18F0x68_LimitCldtCfg_OFFSET 15
#define D18F0x68_LimitCldtCfg_WIDTH 1
#define D18F0x68_LimitCldtCfg_MASK 0x8000
#define D18F0x68_LintEn_OFFSET 16
#define D18F0x68_LintEn_WIDTH 1
#define D18F0x68_LintEn_MASK 0x10000
#define D18F0x68_ApicExtBrdCst_OFFSET 17
#define D18F0x68_ApicExtBrdCst_WIDTH 1
#define D18F0x68_ApicExtBrdCst_MASK 0x20000
#define D18F0x68_ApicExtId_OFFSET 18
#define D18F0x68_ApicExtId_WIDTH 1
#define D18F0x68_ApicExtId_MASK 0x40000
#define D18F0x68_ApicExtSpur_OFFSET 19
#define D18F0x68_ApicExtSpur_WIDTH 1
#define D18F0x68_ApicExtSpur_MASK 0x80000
#define D18F0x68_SeqIdSrcNodeEn_OFFSET 20
#define D18F0x68_SeqIdSrcNodeEn_WIDTH 1
#define D18F0x68_SeqIdSrcNodeEn_MASK 0x100000
#define D18F0x68_DsNpReqLmt_OFFSET 21
#define D18F0x68_DsNpReqLmt_WIDTH 2
#define D18F0x68_DsNpReqLmt_MASK 0x600000
#define D18F0x68_Reserved_31_23_OFFSET 23
#define D18F0x68_Reserved_31_23_WIDTH 9
#define D18F0x68_Reserved_31_23_MASK 0xff800000
/// D18F0x68
typedef union {
struct { ///<
UINT32 Reserved_3_0:4 ; ///<
UINT32 DisMTS:1 ; ///<
UINT32 Reserved_5_5:1 ; ///<
UINT32 CPUReqPassPW:1 ; ///<
UINT32 CPURdRspPassPW:1 ; ///<
UINT32 DisPMemC:1 ; ///<
UINT32 DisRmtPMemC:1 ; ///<
UINT32 DisFillP:1 ; ///<
UINT32 RespPassPW:1 ; ///<
UINT32 Reserved_14_12:3 ; ///<
UINT32 LimitCldtCfg:1 ; ///<
UINT32 LintEn:1 ; ///<
UINT32 ApicExtBrdCst:1 ; ///<
UINT32 ApicExtId:1 ; ///<
UINT32 ApicExtSpur:1 ; ///<
UINT32 SeqIdSrcNodeEn:1 ; ///<
UINT32 DsNpReqLmt:2 ; ///<
UINT32 Reserved_31_23:9 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x68_STRUCT;
// **** D18F0x6C Register Definition ****
// Address
#define D18F0x6C_ADDRESS 0x6c
// Type
#define D18F0x6C_TYPE TYPE_D18F0
// Field Data
#define D18F0x6C_RouteTblDis_OFFSET 0
#define D18F0x6C_RouteTblDis_WIDTH 1
#define D18F0x6C_RouteTblDis_MASK 0x1
#define D18F0x6C_Reserved_3_1_OFFSET 1
#define D18F0x6C_Reserved_3_1_WIDTH 3
#define D18F0x6C_Reserved_3_1_MASK 0xe
#define D18F0x6C_ColdRstDet_OFFSET 4
#define D18F0x6C_ColdRstDet_WIDTH 1
#define D18F0x6C_ColdRstDet_MASK 0x10
#define D18F0x6C_BiosRstDet_0__OFFSET 5
#define D18F0x6C_BiosRstDet_0__WIDTH 1
#define D18F0x6C_BiosRstDet_0__MASK 0x20
#define D18F0x6C_InitDet_OFFSET 6
#define D18F0x6C_InitDet_WIDTH 1
#define D18F0x6C_InitDet_MASK 0x40
#define D18F0x6C_Reserved_8_7_OFFSET 7
#define D18F0x6C_Reserved_8_7_WIDTH 2
#define D18F0x6C_Reserved_8_7_MASK 0x180
#define D18F0x6C_BiosRstDet_2_1__OFFSET 9
#define D18F0x6C_BiosRstDet_2_1__WIDTH 2
#define D18F0x6C_BiosRstDet_2_1__MASK 0x600
#define D18F0x6C_Reserved_26_11_OFFSET 11
#define D18F0x6C_Reserved_26_11_WIDTH 16
#define D18F0x6C_Reserved_26_11_MASK 0x7fff800
#define D18F0x6C_ApplyIsocModeEnNow_OFFSET 27
#define D18F0x6C_ApplyIsocModeEnNow_WIDTH 1
#define D18F0x6C_ApplyIsocModeEnNow_MASK 0x8000000
#define D18F0x6C_RlsIntFullTokCntImm_OFFSET 28
#define D18F0x6C_RlsIntFullTokCntImm_WIDTH 1
#define D18F0x6C_RlsIntFullTokCntImm_MASK 0x10000000
#define D18F0x6C_Reserved_29_29_OFFSET 29
#define D18F0x6C_Reserved_29_29_WIDTH 1
#define D18F0x6C_Reserved_29_29_MASK 0x20000000
#define D18F0x6C_RlsLnkFullTokCntImm_OFFSET 30
#define D18F0x6C_RlsLnkFullTokCntImm_WIDTH 1
#define D18F0x6C_RlsLnkFullTokCntImm_MASK 0x40000000
#define D18F0x6C_Reserved_31_31_OFFSET 31
#define D18F0x6C_Reserved_31_31_WIDTH 1
#define D18F0x6C_Reserved_31_31_MASK 0x80000000
/// D18F0x6C
typedef union {
struct { ///<
UINT32 RouteTblDis:1 ; ///<
UINT32 Reserved_3_1:3 ; ///<
UINT32 ColdRstDet:1 ; ///<
UINT32 BiosRstDet_0_:1 ; ///<
UINT32 InitDet:1 ; ///<
UINT32 Reserved_8_7:2 ; ///<
UINT32 BiosRstDet_2_1_:2 ; ///<
UINT32 Reserved_26_11:16; ///<
UINT32 ApplyIsocModeEnNow:1 ; ///<
UINT32 RlsIntFullTokCntImm:1 ; ///<
UINT32 Reserved_29_29:1 ; ///<
UINT32 RlsLnkFullTokCntImm:1 ; ///<
UINT32 Reserved_31_31:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x6C_STRUCT;
// **** D18F0x84 Register Definition ****
// Address
#define D18F0x84_ADDRESS 0x84
// Type
#define D18F0x84_TYPE TYPE_D18F0
// Field Data
#define D18F0x84_Reserved_3_0_OFFSET 0
#define D18F0x84_Reserved_3_0_WIDTH 4
#define D18F0x84_Reserved_3_0_MASK 0xf
#define D18F0x84_LinkFail_OFFSET 4
#define D18F0x84_LinkFail_WIDTH 1
#define D18F0x84_LinkFail_MASK 0x10
#define D18F0x84_Reserved_5_5_OFFSET 5
#define D18F0x84_Reserved_5_5_WIDTH 1
#define D18F0x84_Reserved_5_5_MASK 0x20
#define D18F0x84_Reserved_11_6_OFFSET 6
#define D18F0x84_Reserved_11_6_WIDTH 6
#define D18F0x84_Reserved_11_6_MASK 0xfc0
#define D18F0x84_IsocEn_OFFSET 12
#define D18F0x84_IsocEn_WIDTH 1
#define D18F0x84_IsocEn_MASK 0x1000
#define D18F0x84_Reserved_31_13_OFFSET 13
#define D18F0x84_Reserved_31_13_WIDTH 19
#define D18F0x84_Reserved_31_13_MASK 0xffffe000
/// D18F0x84
typedef union {
struct { ///<
UINT32 Reserved_3_0:4 ; ///<
UINT32 LinkFail:1 ; ///<
UINT32 Reserved_5_5:1 ; ///<
UINT32 Reserved_11_6:6 ; ///<
UINT32 IsocEn:1 ; ///<
UINT32 Reserved_31_13:19; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x84_STRUCT;
// **** D18F0x90 Register Definition ****
// Address
#define D18F0x90_ADDRESS 0x90
// Type
#define D18F0x90_TYPE TYPE_D18F0
// Field Data
#define D18F0x90_NpReqCmd_OFFSET 0
#define D18F0x90_NpReqCmd_WIDTH 5
#define D18F0x90_NpReqCmd_MASK 0x1f
#define D18F0x90_PReq_OFFSET 5
#define D18F0x90_PReq_WIDTH 3
#define D18F0x90_PReq_MASK 0xe0
#define D18F0x90_RspCmd_OFFSET 8
#define D18F0x90_RspCmd_WIDTH 4
#define D18F0x90_RspCmd_MASK 0xf00
#define D18F0x90_ProbeCmd_OFFSET 12
#define D18F0x90_ProbeCmd_WIDTH 4
#define D18F0x90_ProbeCmd_MASK 0xf000
#define D18F0x90_NpReqData_OFFSET 16
#define D18F0x90_NpReqData_WIDTH 2
#define D18F0x90_NpReqData_MASK 0x30000
#define D18F0x90_RspData_OFFSET 18
#define D18F0x90_RspData_WIDTH 2
#define D18F0x90_RspData_MASK 0xc0000
#define D18F0x90_FreeCmd_OFFSET 20
#define D18F0x90_FreeCmd_WIDTH 5
#define D18F0x90_FreeCmd_MASK 0x1f00000
#define D18F0x90_FreeData_OFFSET 25
#define D18F0x90_FreeData_WIDTH 3
#define D18F0x90_FreeData_MASK 0xe000000
#define D18F0x90_Reserved_30_28_OFFSET 28
#define D18F0x90_Reserved_30_28_WIDTH 3
#define D18F0x90_Reserved_30_28_MASK 0x70000000
#define D18F0x90_LockBc_OFFSET 31
#define D18F0x90_LockBc_WIDTH 1
#define D18F0x90_LockBc_MASK 0x80000000
/// D18F0x90
typedef union {
struct { ///<
UINT32 NpReqCmd:5 ; ///<
UINT32 PReq:3 ; ///<
UINT32 RspCmd:4 ; ///<
UINT32 ProbeCmd:4 ; ///<
UINT32 NpReqData:2 ; ///<
UINT32 RspData:2 ; ///<
UINT32 FreeCmd:5 ; ///<
UINT32 FreeData:3 ; ///<
UINT32 Reserved_30_28:3 ; ///<
UINT32 LockBc:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x90_STRUCT;
// **** D18F0x94 Register Definition ****
// Address
#define D18F0x94_ADDRESS 0x94
// Type
#define D18F0x94_TYPE TYPE_D18F0
// Field Data
#define D18F0x94_Reserved_7_0_OFFSET 0
#define D18F0x94_Reserved_7_0_WIDTH 8
#define D18F0x94_Reserved_7_0_MASK 0xff
#define D18F0x94_SecBusNum_OFFSET 8
#define D18F0x94_SecBusNum_WIDTH 8
#define D18F0x94_SecBusNum_MASK 0xff00
#define D18F0x94_IsocNpReqCmd_OFFSET 16
#define D18F0x94_IsocNpReqCmd_WIDTH 3
#define D18F0x94_IsocNpReqCmd_MASK 0x70000
#define D18F0x94_IsocPReq_OFFSET 19
#define D18F0x94_IsocPReq_WIDTH 3
#define D18F0x94_IsocPReq_MASK 0x380000
#define D18F0x94_IsocRspCmd_OFFSET 22
#define D18F0x94_IsocRspCmd_WIDTH 3
#define D18F0x94_IsocRspCmd_MASK 0x1c00000
#define D18F0x94_IsocNpReqData_OFFSET 25
#define D18F0x94_IsocNpReqData_WIDTH 2
#define D18F0x94_IsocNpReqData_MASK 0x6000000
#define D18F0x94_IsocRspData_OFFSET 27
#define D18F0x94_IsocRspData_WIDTH 2
#define D18F0x94_IsocRspData_MASK 0x18000000
#define D18F0x94_Reserved_31_29_OFFSET 29
#define D18F0x94_Reserved_31_29_WIDTH 3
#define D18F0x94_Reserved_31_29_MASK 0xe0000000
/// D18F0x94
typedef union {
struct { ///<
UINT32 Reserved_7_0:8 ; ///<
UINT32 SecBusNum:8 ; ///<
UINT32 IsocNpReqCmd:3 ; ///<
UINT32 IsocPReq:3 ; ///<
UINT32 IsocRspCmd:3 ; ///<
UINT32 IsocNpReqData:2 ; ///<
UINT32 IsocRspData:2 ; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x94_STRUCT;
// **** D18F0x98 Register Definition ****
// Address
#define D18F0x98_ADDRESS 0x98
// Type
#define D18F0x98_TYPE TYPE_D18F0
// Field Data
#define D18F0x98_Reserved_0_0_OFFSET 0
#define D18F0x98_Reserved_0_0_WIDTH 1
#define D18F0x98_Reserved_0_0_MASK 0x1
#define D18F0x98_Reserved_1_1_OFFSET 1
#define D18F0x98_Reserved_1_1_WIDTH 1
#define D18F0x98_Reserved_1_1_MASK 0x2
#define D18F0x98_Reserved_2_2_OFFSET 2
#define D18F0x98_Reserved_2_2_WIDTH 1
#define D18F0x98_Reserved_2_2_MASK 0x4
#define D18F0x98_Reserved_4_3_OFFSET 3
#define D18F0x98_Reserved_4_3_WIDTH 2
#define D18F0x98_Reserved_4_3_MASK 0x18
#define D18F0x98_PciEligible_OFFSET 5
#define D18F0x98_PciEligible_WIDTH 1
#define D18F0x98_PciEligible_MASK 0x20
#define D18F0x98_Reserved_31_6_OFFSET 6
#define D18F0x98_Reserved_31_6_WIDTH 26
#define D18F0x98_Reserved_31_6_MASK 0xffffffc0
/// D18F0x98
typedef union {
struct { ///<
UINT32 Reserved_0_0:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Reserved_4_3:2 ; ///<
UINT32 PciEligible:1 ; ///<
UINT32 Reserved_31_6:26; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x98_STRUCT;
// **** D18F0x9C Register Definition ****
// Address
#define D18F0x9C_ADDRESS 0x9c
// Type
#define D18F0x9C_TYPE TYPE_D18F0
// Field Data
#define D18F0x9C_Reserved_0_0_OFFSET 0
#define D18F0x9C_Reserved_0_0_WIDTH 1
#define D18F0x9C_Reserved_0_0_MASK 0x1
#define D18F0x9C_Reserved_15_1_OFFSET 1
#define D18F0x9C_Reserved_15_1_WIDTH 15
#define D18F0x9C_Reserved_15_1_MASK 0xfffe
#define D18F0x9C_Reserved_31_16_OFFSET 16
#define D18F0x9C_Reserved_31_16_WIDTH 16
#define D18F0x9C_Reserved_31_16_MASK 0xffff0000
/// D18F0x9C
typedef union {
struct { ///<
UINT32 Reserved_0_0:1 ; ///<
UINT32 Reserved_15_1:15; ///<
UINT32 Reserved_31_16:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x9C_STRUCT;
// **** D18F0x110 Register Definition ****
// Address
#define D18F0x110_ADDRESS 0x110
// Type
#define D18F0x110_TYPE TYPE_D18F0
// Field Data
#define D18F0x110_Reserved_0_0_OFFSET 0
#define D18F0x110_Reserved_0_0_WIDTH 1
#define D18F0x110_Reserved_0_0_MASK 0x1
#define D18F0x110_Reserved_1_1_OFFSET 1
#define D18F0x110_Reserved_1_1_WIDTH 1
#define D18F0x110_Reserved_1_1_MASK 0x2
#define D18F0x110_ClumpEn_OFFSET 2
#define D18F0x110_ClumpEn_WIDTH 30
#define D18F0x110_ClumpEn_MASK 0xfffffffc
/// D18F0x110
typedef union {
struct { ///<
UINT32 Reserved_0_0:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 ClumpEn:30; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x110_STRUCT;
// **** D18F0x16C Register Definition ****
// Address
#define D18F0x16C_ADDRESS 0x16c
// Type
#define D18F0x16C_TYPE TYPE_D18F0
// Field Data
#define D18F0x16C_Reserved_31_0_OFFSET 0
#define D18F0x16C_Reserved_31_0_WIDTH 32
#define D18F0x16C_Reserved_31_0_MASK 0xffffffff
/// D18F0x16C
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x16C_STRUCT;
// **** D18F0x170 Register Definition ****
// Address
#define D18F0x170_ADDRESS 0x170
// Type
#define D18F0x170_TYPE TYPE_D18F0
// Field Data
#define D18F0x170_Reserved_31_0_OFFSET 0
#define D18F0x170_Reserved_31_0_WIDTH 32
#define D18F0x170_Reserved_31_0_MASK 0xffffffff
/// D18F0x170
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x170_STRUCT;
// **** D18F0x1A0 Register Definition ****
// Address
#define D18F0x1A0_ADDRESS 0x1a0
// Type
#define D18F0x1A0_TYPE TYPE_D18F0
// Field Data
#define D18F0x1A0_InitComplete_OFFSET 0
#define D18F0x1A0_InitComplete_WIDTH 2
#define D18F0x1A0_InitComplete_MASK 0x3
#define D18F0x1A0_Reserved_30_2_OFFSET 2
#define D18F0x1A0_Reserved_30_2_WIDTH 29
#define D18F0x1A0_Reserved_30_2_MASK 0x7ffffffc
#define D18F0x1A0_InitStatusValid_OFFSET 31
#define D18F0x1A0_InitStatusValid_WIDTH 1
#define D18F0x1A0_InitStatusValid_MASK 0x80000000
/// D18F0x1A0
typedef union {
struct { ///<
UINT32 InitComplete:2 ; ///<
UINT32 Reserved_30_2:29; ///<
UINT32 InitStatusValid:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x1A0_STRUCT;
// **** D18F0x1DC Register Definition ****
// Address
#define D18F0x1DC_ADDRESS 0x1dc
// Type
#define D18F0x1DC_TYPE TYPE_D18F0
// Field Data
#define D18F0x1DC_Reserved_0_0_OFFSET 0
#define D18F0x1DC_Reserved_0_0_WIDTH 1
#define D18F0x1DC_Reserved_0_0_MASK 0x1
#define D18F0x1DC_CpuEn_OFFSET 1
#define D18F0x1DC_CpuEn_WIDTH 7
#define D18F0x1DC_CpuEn_MASK 0xfe
#define D18F0x1DC_Reserved_31_8_OFFSET 8
#define D18F0x1DC_Reserved_31_8_WIDTH 24
#define D18F0x1DC_Reserved_31_8_MASK 0xffffff00
/// D18F0x1DC
typedef union {
struct { ///<
UINT32 Reserved_0_0:1 ; ///<
UINT32 CpuEn:7 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F0x1DC_STRUCT;
// **** D18F1x00 Register Definition ****
// Address
#define D18F1x00_ADDRESS 0x0
// Type
#define D18F1x00_TYPE TYPE_D18F1
// Field Data
#define D18F1x00_VendorID_OFFSET 0
#define D18F1x00_VendorID_WIDTH 16
#define D18F1x00_VendorID_MASK 0xffff
#define D18F1x00_DeviceID_OFFSET 16
#define D18F1x00_DeviceID_WIDTH 16
#define D18F1x00_DeviceID_MASK 0xffff0000
/// D18F1x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x00_STRUCT;
// **** D18F1x08 Register Definition ****
// Address
#define D18F1x08_ADDRESS 0x8
// Type
#define D18F1x08_TYPE TYPE_D18F1
// Field Data
#define D18F1x08_RevID_OFFSET 0
#define D18F1x08_RevID_WIDTH 8
#define D18F1x08_RevID_MASK 0xff
#define D18F1x08_ClassCode_OFFSET 8
#define D18F1x08_ClassCode_WIDTH 24
#define D18F1x08_ClassCode_MASK 0xffffff00
/// D18F1x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x08_STRUCT;
// **** D18F1x0C Register Definition ****
// Address
#define D18F1x0C_ADDRESS 0xc
// Type
#define D18F1x0C_TYPE TYPE_D18F1
// Field Data
#define D18F1x0C_HeaderTypeReg_OFFSET 0
#define D18F1x0C_HeaderTypeReg_WIDTH 32
#define D18F1x0C_HeaderTypeReg_MASK 0xffffffff
/// D18F1x0C
typedef union {
struct { ///<
UINT32 HeaderTypeReg:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x0C_STRUCT;
// **** D18F1x40 Register Definition ****
// Address
#define D18F1x40_ADDRESS 0x40
// Type
#define D18F1x40_TYPE TYPE_D18F1
// Field Data
#define D18F1x40_RE_OFFSET 0
#define D18F1x40_RE_WIDTH 1
#define D18F1x40_RE_MASK 0x1
#define D18F1x40_WE_OFFSET 1
#define D18F1x40_WE_WIDTH 1
#define D18F1x40_WE_MASK 0x2
#define D18F1x40_Reserved_15_2_OFFSET 2
#define D18F1x40_Reserved_15_2_WIDTH 14
#define D18F1x40_Reserved_15_2_MASK 0xfffc
#define D18F1x40_DramBase_39_24__OFFSET 16
#define D18F1x40_DramBase_39_24__WIDTH 16
#define D18F1x40_DramBase_39_24__MASK 0xffff0000
/// D18F1x40
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_15_2:14; ///<
UINT32 DramBase_39_24_:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x40_STRUCT;
// **** D18F1x44 Register Definition ****
// Address
#define D18F1x44_ADDRESS 0x44
// Type
#define D18F1x44_TYPE TYPE_D18F1
// Field Data
#define D18F1x44_DstNode_OFFSET 0
#define D18F1x44_DstNode_WIDTH 3
#define D18F1x44_DstNode_MASK 0x7
#define D18F1x44_Reserved_7_3_OFFSET 3
#define D18F1x44_Reserved_7_3_WIDTH 5
#define D18F1x44_Reserved_7_3_MASK 0xf8
#define D18F1x44_Reserved_10_8_OFFSET 8
#define D18F1x44_Reserved_10_8_WIDTH 3
#define D18F1x44_Reserved_10_8_MASK 0x700
#define D18F1x44_Reserved_15_11_OFFSET 11
#define D18F1x44_Reserved_15_11_WIDTH 5
#define D18F1x44_Reserved_15_11_MASK 0xf800
#define D18F1x44_DramLimit_39_24__OFFSET 16
#define D18F1x44_DramLimit_39_24__WIDTH 16
#define D18F1x44_DramLimit_39_24__MASK 0xffff0000
/// D18F1x44
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_7_3:5 ; ///<
UINT32 Reserved_10_8:3 ; ///<
UINT32 Reserved_15_11:5 ; ///<
UINT32 DramLimit_39_24_:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x44_STRUCT;
// **** D18F1x80 Register Definition ****
// Address
#define D18F1x80_ADDRESS 0x80
// Type
#define D18F1x80_TYPE TYPE_D18F1
// Field Data
#define D18F1x80_RE_OFFSET 0
#define D18F1x80_RE_WIDTH 1
#define D18F1x80_RE_MASK 0x1
#define D18F1x80_WE_OFFSET 1
#define D18F1x80_WE_WIDTH 1
#define D18F1x80_WE_MASK 0x2
#define D18F1x80_Reserved_2_2_OFFSET 2
#define D18F1x80_Reserved_2_2_WIDTH 1
#define D18F1x80_Reserved_2_2_MASK 0x4
#define D18F1x80_Lock_OFFSET 3
#define D18F1x80_Lock_WIDTH 1
#define D18F1x80_Lock_MASK 0x8
#define D18F1x80_Reserved_7_4_OFFSET 4
#define D18F1x80_Reserved_7_4_WIDTH 4
#define D18F1x80_Reserved_7_4_MASK 0xf0
#define D18F1x80_MMIOBase_39_16__OFFSET 8
#define D18F1x80_MMIOBase_39_16__WIDTH 24
#define D18F1x80_MMIOBase_39_16__MASK 0xffffff00
/// D18F1x80
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x80_STRUCT;
// **** D18F1x84 Register Definition ****
// Address
#define D18F1x84_ADDRESS 0x84
// Type
#define D18F1x84_TYPE TYPE_D18F1
// Field Data
#define D18F1x84_DstNode_OFFSET 0
#define D18F1x84_DstNode_WIDTH 3
#define D18F1x84_DstNode_MASK 0x7
#define D18F1x84_Reserved_3_3_OFFSET 3
#define D18F1x84_Reserved_3_3_WIDTH 1
#define D18F1x84_Reserved_3_3_MASK 0x8
#define D18F1x84_DstLink_OFFSET 4
#define D18F1x84_DstLink_WIDTH 2
#define D18F1x84_DstLink_MASK 0x30
#define D18F1x84_DstSubLink_OFFSET 6
#define D18F1x84_DstSubLink_WIDTH 1
#define D18F1x84_DstSubLink_MASK 0x40
#define D18F1x84_NP_OFFSET 7
#define D18F1x84_NP_WIDTH 1
#define D18F1x84_NP_MASK 0x80
#define D18F1x84_MMIOLimit_39_16__OFFSET 8
#define D18F1x84_MMIOLimit_39_16__WIDTH 24
#define D18F1x84_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1x84
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x84_STRUCT;
// **** D18F1x88 Register Definition ****
// Address
#define D18F1x88_ADDRESS 0x88
// Type
#define D18F1x88_TYPE TYPE_D18F1
// Field Data
#define D18F1x88_RE_OFFSET 0
#define D18F1x88_RE_WIDTH 1
#define D18F1x88_RE_MASK 0x1
#define D18F1x88_WE_OFFSET 1
#define D18F1x88_WE_WIDTH 1
#define D18F1x88_WE_MASK 0x2
#define D18F1x88_Reserved_2_2_OFFSET 2
#define D18F1x88_Reserved_2_2_WIDTH 1
#define D18F1x88_Reserved_2_2_MASK 0x4
#define D18F1x88_Lock_OFFSET 3
#define D18F1x88_Lock_WIDTH 1
#define D18F1x88_Lock_MASK 0x8
#define D18F1x88_Reserved_7_4_OFFSET 4
#define D18F1x88_Reserved_7_4_WIDTH 4
#define D18F1x88_Reserved_7_4_MASK 0xf0
#define D18F1x88_MMIOBase_39_16__OFFSET 8
#define D18F1x88_MMIOBase_39_16__WIDTH 24
#define D18F1x88_MMIOBase_39_16__MASK 0xffffff00
/// D18F1x88
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x88_STRUCT;
// **** D18F1x8C Register Definition ****
// Address
#define D18F1x8C_ADDRESS 0x8c
// Type
#define D18F1x8C_TYPE TYPE_D18F1
// Field Data
#define D18F1x8C_DstNode_OFFSET 0
#define D18F1x8C_DstNode_WIDTH 3
#define D18F1x8C_DstNode_MASK 0x7
#define D18F1x8C_Reserved_3_3_OFFSET 3
#define D18F1x8C_Reserved_3_3_WIDTH 1
#define D18F1x8C_Reserved_3_3_MASK 0x8
#define D18F1x8C_DstLink_OFFSET 4
#define D18F1x8C_DstLink_WIDTH 2
#define D18F1x8C_DstLink_MASK 0x30
#define D18F1x8C_DstSubLink_OFFSET 6
#define D18F1x8C_DstSubLink_WIDTH 1
#define D18F1x8C_DstSubLink_MASK 0x40
#define D18F1x8C_NP_OFFSET 7
#define D18F1x8C_NP_WIDTH 1
#define D18F1x8C_NP_MASK 0x80
#define D18F1x8C_MMIOLimit_39_16__OFFSET 8
#define D18F1x8C_MMIOLimit_39_16__WIDTH 24
#define D18F1x8C_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1x8C
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x8C_STRUCT;
// **** D18F1x90 Register Definition ****
// Address
#define D18F1x90_ADDRESS 0x90
// Type
#define D18F1x90_TYPE TYPE_D18F1
// Field Data
#define D18F1x90_RE_OFFSET 0
#define D18F1x90_RE_WIDTH 1
#define D18F1x90_RE_MASK 0x1
#define D18F1x90_WE_OFFSET 1
#define D18F1x90_WE_WIDTH 1
#define D18F1x90_WE_MASK 0x2
#define D18F1x90_Reserved_2_2_OFFSET 2
#define D18F1x90_Reserved_2_2_WIDTH 1
#define D18F1x90_Reserved_2_2_MASK 0x4
#define D18F1x90_Lock_OFFSET 3
#define D18F1x90_Lock_WIDTH 1
#define D18F1x90_Lock_MASK 0x8
#define D18F1x90_Reserved_7_4_OFFSET 4
#define D18F1x90_Reserved_7_4_WIDTH 4
#define D18F1x90_Reserved_7_4_MASK 0xf0
#define D18F1x90_MMIOBase_39_16__OFFSET 8
#define D18F1x90_MMIOBase_39_16__WIDTH 24
#define D18F1x90_MMIOBase_39_16__MASK 0xffffff00
/// D18F1x90
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x90_STRUCT;
// **** D18F1x94 Register Definition ****
// Address
#define D18F1x94_ADDRESS 0x94
// Type
#define D18F1x94_TYPE TYPE_D18F1
// Field Data
#define D18F1x94_DstNode_OFFSET 0
#define D18F1x94_DstNode_WIDTH 3
#define D18F1x94_DstNode_MASK 0x7
#define D18F1x94_Reserved_3_3_OFFSET 3
#define D18F1x94_Reserved_3_3_WIDTH 1
#define D18F1x94_Reserved_3_3_MASK 0x8
#define D18F1x94_DstLink_OFFSET 4
#define D18F1x94_DstLink_WIDTH 2
#define D18F1x94_DstLink_MASK 0x30
#define D18F1x94_DstSubLink_OFFSET 6
#define D18F1x94_DstSubLink_WIDTH 1
#define D18F1x94_DstSubLink_MASK 0x40
#define D18F1x94_NP_OFFSET 7
#define D18F1x94_NP_WIDTH 1
#define D18F1x94_NP_MASK 0x80
#define D18F1x94_MMIOLimit_39_16__OFFSET 8
#define D18F1x94_MMIOLimit_39_16__WIDTH 24
#define D18F1x94_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1x94
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x94_STRUCT;
// **** D18F1x98 Register Definition ****
// Address
#define D18F1x98_ADDRESS 0x98
// Type
#define D18F1x98_TYPE TYPE_D18F1
// Field Data
#define D18F1x98_RE_OFFSET 0
#define D18F1x98_RE_WIDTH 1
#define D18F1x98_RE_MASK 0x1
#define D18F1x98_WE_OFFSET 1
#define D18F1x98_WE_WIDTH 1
#define D18F1x98_WE_MASK 0x2
#define D18F1x98_Reserved_2_2_OFFSET 2
#define D18F1x98_Reserved_2_2_WIDTH 1
#define D18F1x98_Reserved_2_2_MASK 0x4
#define D18F1x98_Lock_OFFSET 3
#define D18F1x98_Lock_WIDTH 1
#define D18F1x98_Lock_MASK 0x8
#define D18F1x98_Reserved_7_4_OFFSET 4
#define D18F1x98_Reserved_7_4_WIDTH 4
#define D18F1x98_Reserved_7_4_MASK 0xf0
#define D18F1x98_MMIOBase_39_16__OFFSET 8
#define D18F1x98_MMIOBase_39_16__WIDTH 24
#define D18F1x98_MMIOBase_39_16__MASK 0xffffff00
/// D18F1x98
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x98_STRUCT;
// **** D18F1x9C Register Definition ****
// Address
#define D18F1x9C_ADDRESS 0x9c
// Type
#define D18F1x9C_TYPE TYPE_D18F1
// Field Data
#define D18F1x9C_DstNode_OFFSET 0
#define D18F1x9C_DstNode_WIDTH 3
#define D18F1x9C_DstNode_MASK 0x7
#define D18F1x9C_Reserved_3_3_OFFSET 3
#define D18F1x9C_Reserved_3_3_WIDTH 1
#define D18F1x9C_Reserved_3_3_MASK 0x8
#define D18F1x9C_DstLink_OFFSET 4
#define D18F1x9C_DstLink_WIDTH 2
#define D18F1x9C_DstLink_MASK 0x30
#define D18F1x9C_DstSubLink_OFFSET 6
#define D18F1x9C_DstSubLink_WIDTH 1
#define D18F1x9C_DstSubLink_MASK 0x40
#define D18F1x9C_NP_OFFSET 7
#define D18F1x9C_NP_WIDTH 1
#define D18F1x9C_NP_MASK 0x80
#define D18F1x9C_MMIOLimit_39_16__OFFSET 8
#define D18F1x9C_MMIOLimit_39_16__WIDTH 24
#define D18F1x9C_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1x9C
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1x9C_STRUCT;
// **** D18F1xA0 Register Definition ****
// Address
#define D18F1xA0_ADDRESS 0xa0
// Type
#define D18F1xA0_TYPE TYPE_D18F1
// Field Data
#define D18F1xA0_RE_OFFSET 0
#define D18F1xA0_RE_WIDTH 1
#define D18F1xA0_RE_MASK 0x1
#define D18F1xA0_WE_OFFSET 1
#define D18F1xA0_WE_WIDTH 1
#define D18F1xA0_WE_MASK 0x2
#define D18F1xA0_Reserved_2_2_OFFSET 2
#define D18F1xA0_Reserved_2_2_WIDTH 1
#define D18F1xA0_Reserved_2_2_MASK 0x4
#define D18F1xA0_Lock_OFFSET 3
#define D18F1xA0_Lock_WIDTH 1
#define D18F1xA0_Lock_MASK 0x8
#define D18F1xA0_Reserved_7_4_OFFSET 4
#define D18F1xA0_Reserved_7_4_WIDTH 4
#define D18F1xA0_Reserved_7_4_MASK 0xf0
#define D18F1xA0_MMIOBase_39_16__OFFSET 8
#define D18F1xA0_MMIOBase_39_16__WIDTH 24
#define D18F1xA0_MMIOBase_39_16__MASK 0xffffff00
/// D18F1xA0
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xA0_STRUCT;
// **** D18F1xA4 Register Definition ****
// Address
#define D18F1xA4_ADDRESS 0xa4
// Type
#define D18F1xA4_TYPE TYPE_D18F1
// Field Data
#define D18F1xA4_DstNode_OFFSET 0
#define D18F1xA4_DstNode_WIDTH 3
#define D18F1xA4_DstNode_MASK 0x7
#define D18F1xA4_Reserved_3_3_OFFSET 3
#define D18F1xA4_Reserved_3_3_WIDTH 1
#define D18F1xA4_Reserved_3_3_MASK 0x8
#define D18F1xA4_DstLink_OFFSET 4
#define D18F1xA4_DstLink_WIDTH 2
#define D18F1xA4_DstLink_MASK 0x30
#define D18F1xA4_DstSubLink_OFFSET 6
#define D18F1xA4_DstSubLink_WIDTH 1
#define D18F1xA4_DstSubLink_MASK 0x40
#define D18F1xA4_NP_OFFSET 7
#define D18F1xA4_NP_WIDTH 1
#define D18F1xA4_NP_MASK 0x80
#define D18F1xA4_MMIOLimit_39_16__OFFSET 8
#define D18F1xA4_MMIOLimit_39_16__WIDTH 24
#define D18F1xA4_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1xA4
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xA4_STRUCT;
// **** D18F1xA8 Register Definition ****
// Address
#define D18F1xA8_ADDRESS 0xa8
// Type
#define D18F1xA8_TYPE TYPE_D18F1
// Field Data
#define D18F1xA8_RE_OFFSET 0
#define D18F1xA8_RE_WIDTH 1
#define D18F1xA8_RE_MASK 0x1
#define D18F1xA8_WE_OFFSET 1
#define D18F1xA8_WE_WIDTH 1
#define D18F1xA8_WE_MASK 0x2
#define D18F1xA8_Reserved_2_2_OFFSET 2
#define D18F1xA8_Reserved_2_2_WIDTH 1
#define D18F1xA8_Reserved_2_2_MASK 0x4
#define D18F1xA8_Lock_OFFSET 3
#define D18F1xA8_Lock_WIDTH 1
#define D18F1xA8_Lock_MASK 0x8
#define D18F1xA8_Reserved_7_4_OFFSET 4
#define D18F1xA8_Reserved_7_4_WIDTH 4
#define D18F1xA8_Reserved_7_4_MASK 0xf0
#define D18F1xA8_MMIOBase_39_16__OFFSET 8
#define D18F1xA8_MMIOBase_39_16__WIDTH 24
#define D18F1xA8_MMIOBase_39_16__MASK 0xffffff00
/// D18F1xA8
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xA8_STRUCT;
// **** D18F1xAC Register Definition ****
// Address
#define D18F1xAC_ADDRESS 0xac
// Type
#define D18F1xAC_TYPE TYPE_D18F1
// Field Data
#define D18F1xAC_DstNode_OFFSET 0
#define D18F1xAC_DstNode_WIDTH 3
#define D18F1xAC_DstNode_MASK 0x7
#define D18F1xAC_Reserved_3_3_OFFSET 3
#define D18F1xAC_Reserved_3_3_WIDTH 1
#define D18F1xAC_Reserved_3_3_MASK 0x8
#define D18F1xAC_DstLink_OFFSET 4
#define D18F1xAC_DstLink_WIDTH 2
#define D18F1xAC_DstLink_MASK 0x30
#define D18F1xAC_DstSubLink_OFFSET 6
#define D18F1xAC_DstSubLink_WIDTH 1
#define D18F1xAC_DstSubLink_MASK 0x40
#define D18F1xAC_NP_OFFSET 7
#define D18F1xAC_NP_WIDTH 1
#define D18F1xAC_NP_MASK 0x80
#define D18F1xAC_MMIOLimit_39_16__OFFSET 8
#define D18F1xAC_MMIOLimit_39_16__WIDTH 24
#define D18F1xAC_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1xAC
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xAC_STRUCT;
// **** D18F1xB0 Register Definition ****
// Address
#define D18F1xB0_ADDRESS 0xb0
// Type
#define D18F1xB0_TYPE TYPE_D18F1
// Field Data
#define D18F1xB0_RE_OFFSET 0
#define D18F1xB0_RE_WIDTH 1
#define D18F1xB0_RE_MASK 0x1
#define D18F1xB0_WE_OFFSET 1
#define D18F1xB0_WE_WIDTH 1
#define D18F1xB0_WE_MASK 0x2
#define D18F1xB0_Reserved_2_2_OFFSET 2
#define D18F1xB0_Reserved_2_2_WIDTH 1
#define D18F1xB0_Reserved_2_2_MASK 0x4
#define D18F1xB0_Lock_OFFSET 3
#define D18F1xB0_Lock_WIDTH 1
#define D18F1xB0_Lock_MASK 0x8
#define D18F1xB0_Reserved_7_4_OFFSET 4
#define D18F1xB0_Reserved_7_4_WIDTH 4
#define D18F1xB0_Reserved_7_4_MASK 0xf0
#define D18F1xB0_MMIOBase_39_16__OFFSET 8
#define D18F1xB0_MMIOBase_39_16__WIDTH 24
#define D18F1xB0_MMIOBase_39_16__MASK 0xffffff00
/// D18F1xB0
typedef union {
struct { ///<
UINT32 RE:1 ; ///<
UINT32 WE:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Lock:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 MMIOBase_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xB0_STRUCT;
// **** D18F1xB4 Register Definition ****
// Address
#define D18F1xB4_ADDRESS 0xb4
// Type
#define D18F1xB4_TYPE TYPE_D18F1
// Field Data
#define D18F1xB4_DstNode_OFFSET 0
#define D18F1xB4_DstNode_WIDTH 3
#define D18F1xB4_DstNode_MASK 0x7
#define D18F1xB4_Reserved_3_3_OFFSET 3
#define D18F1xB4_Reserved_3_3_WIDTH 1
#define D18F1xB4_Reserved_3_3_MASK 0x8
#define D18F1xB4_DstLink_OFFSET 4
#define D18F1xB4_DstLink_WIDTH 2
#define D18F1xB4_DstLink_MASK 0x30
#define D18F1xB4_DstSubLink_OFFSET 6
#define D18F1xB4_DstSubLink_WIDTH 1
#define D18F1xB4_DstSubLink_MASK 0x40
#define D18F1xB4_NP_OFFSET 7
#define D18F1xB4_NP_WIDTH 1
#define D18F1xB4_NP_MASK 0x80
#define D18F1xB4_MMIOLimit_39_16__OFFSET 8
#define D18F1xB4_MMIOLimit_39_16__WIDTH 24
#define D18F1xB4_MMIOLimit_39_16__MASK 0xffffff00
/// D18F1xB4
typedef union {
struct { ///<
UINT32 DstNode:3 ; ///<
UINT32 Reserved_3_3:1 ; ///<
UINT32 DstLink:2 ; ///<
UINT32 DstSubLink:1 ; ///<
UINT32 NP:1 ; ///<
UINT32 MMIOLimit_39_16_:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xB4_STRUCT;
// **** D18F1xB8 Register Definition ****
// Address
#define D18F1xB8_ADDRESS 0xb8
// Type
#define D18F1xB8_TYPE TYPE_D18F1
// Field Data
#define D18F1xB8_RE_OFFSET 0
#define D18F1xB8_RE_WIDTH 1
#define D18F1xB8_RE_MASK