blob: e3657eb4ebcd98be59efa512900b739425744e96 [file] [log] [blame]
/* $NoKeywords:$ */
/**
* @file
*
* Register definitions
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _GNBREGISTERSLN_H_
#define _GNBREGISTERSLN_H_
#define TYPE_D0F0 0x1
#define TYPE_D0F0x64 0x2
#define TYPE_D0F0x98 0x3
#define TYPE_D0F0xE4 0x5
#define TYPE_DxF0 0x6
#define TYPE_DxF0xE4 0x7
#define TYPE_D18F1 0xb
#define TYPE_D18F2 0xc
#define TYPE_D18F3 0xd
#define TYPE_MSR 0x10
#define TYPE_D1F0 0x11
#define TYPE_GMM 0x12
#define D18F2x9C 0xe
#define GMM 0x11
#ifndef WRAP_SPACE
#define WRAP_SPACE(w, x) (0x01300000 | (w << 16) | (x))
#endif
#ifndef CORE_SPACE
#define CORE_SPACE(c, x) (0x00010000 | (c << 24) | (x))
#endif
#ifndef PHY_SPACE
#define PHY_SPACE(w, p, x) (0x00200000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
#ifndef PIF_SPACE
#define PIF_SPACE(w, p, x) (0x00100000 | ((p + 1) << 24) | (w << 16) | (x))
#endif
// **** D0F0x00 Register Definition ****
// Address
#define D0F0x00_ADDRESS 0x0
// Type
#define D0F0x00_TYPE TYPE_D0F0
// Field Data
#define D0F0x00_VendorID_OFFSET 0
#define D0F0x00_VendorID_WIDTH 16
#define D0F0x00_VendorID_MASK 0xffff
#define D0F0x00_DeviceID_OFFSET 16
#define D0F0x00_DeviceID_WIDTH 16
#define D0F0x00_DeviceID_MASK 0xffff0000
/// D0F0x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x00_STRUCT;
// **** D0F0x04 Register Definition ****
// Address
#define D0F0x04_ADDRESS 0x4
// Type
#define D0F0x04_TYPE TYPE_D0F0
// Field Data
#define D0F0x04_IoAccessEn_OFFSET 0
#define D0F0x04_IoAccessEn_WIDTH 1
#define D0F0x04_IoAccessEn_MASK 0x1
#define D0F0x04_MemAccessEn_OFFSET 1
#define D0F0x04_MemAccessEn_WIDTH 1
#define D0F0x04_MemAccessEn_MASK 0x2
#define D0F0x04_BusMasterEn_OFFSET 2
#define D0F0x04_BusMasterEn_WIDTH 1
#define D0F0x04_BusMasterEn_MASK 0x4
#define D0F0x04_SpecialCycleEn_OFFSET 3
#define D0F0x04_SpecialCycleEn_WIDTH 1
#define D0F0x04_SpecialCycleEn_MASK 0x8
#define D0F0x04_MemWriteInvalidateEn_OFFSET 4
#define D0F0x04_MemWriteInvalidateEn_WIDTH 1
#define D0F0x04_MemWriteInvalidateEn_MASK 0x10
#define D0F0x04_PalSnoopEn_OFFSET 5
#define D0F0x04_PalSnoopEn_WIDTH 1
#define D0F0x04_PalSnoopEn_MASK 0x20
#define D0F0x04_ParityErrorEn_OFFSET 6
#define D0F0x04_ParityErrorEn_WIDTH 1
#define D0F0x04_ParityErrorEn_MASK 0x40
#define D0F0x04_Reserved_7_7_OFFSET 7
#define D0F0x04_Reserved_7_7_WIDTH 1
#define D0F0x04_Reserved_7_7_MASK 0x80
#define D0F0x04_SerrEn_OFFSET 8
#define D0F0x04_SerrEn_WIDTH 1
#define D0F0x04_SerrEn_MASK 0x100
#define D0F0x04_FastB2BEn_OFFSET 9
#define D0F0x04_FastB2BEn_WIDTH 1
#define D0F0x04_FastB2BEn_MASK 0x200
#define D0F0x04_Reserved_19_10_OFFSET 10
#define D0F0x04_Reserved_19_10_WIDTH 10
#define D0F0x04_Reserved_19_10_MASK 0xffc00
#define D0F0x04_CapList_OFFSET 20
#define D0F0x04_CapList_WIDTH 1
#define D0F0x04_CapList_MASK 0x100000
#define D0F0x04_PCI66En_OFFSET 21
#define D0F0x04_PCI66En_WIDTH 1
#define D0F0x04_PCI66En_MASK 0x200000
#define D0F0x04_Reserved_22_22_OFFSET 22
#define D0F0x04_Reserved_22_22_WIDTH 1
#define D0F0x04_Reserved_22_22_MASK 0x400000
#define D0F0x04_FastBackCapable_OFFSET 23
#define D0F0x04_FastBackCapable_WIDTH 1
#define D0F0x04_FastBackCapable_MASK 0x800000
#define D0F0x04_Reserved_24_24_OFFSET 24
#define D0F0x04_Reserved_24_24_WIDTH 1
#define D0F0x04_Reserved_24_24_MASK 0x1000000
#define D0F0x04_DevselTiming_OFFSET 25
#define D0F0x04_DevselTiming_WIDTH 2
#define D0F0x04_DevselTiming_MASK 0x6000000
#define D0F0x04_SignalTargetAbort_OFFSET 27
#define D0F0x04_SignalTargetAbort_WIDTH 1
#define D0F0x04_SignalTargetAbort_MASK 0x8000000
#define D0F0x04_ReceivedTargetAbort_OFFSET 28
#define D0F0x04_ReceivedTargetAbort_WIDTH 1
#define D0F0x04_ReceivedTargetAbort_MASK 0x10000000
#define D0F0x04_ReceivedMasterAbort_OFFSET 29
#define D0F0x04_ReceivedMasterAbort_WIDTH 1
#define D0F0x04_ReceivedMasterAbort_MASK 0x20000000
#define D0F0x04_SignaledSystemError_OFFSET 30
#define D0F0x04_SignaledSystemError_WIDTH 1
#define D0F0x04_SignaledSystemError_MASK 0x40000000
#define D0F0x04_ParityErrorDetected_OFFSET 31
#define D0F0x04_ParityErrorDetected_WIDTH 1
#define D0F0x04_ParityErrorDetected_MASK 0x80000000
/// D0F0x04
typedef union {
struct { ///<
UINT32 IoAccessEn:1 ; ///<
UINT32 MemAccessEn:1 ; ///<
UINT32 BusMasterEn:1 ; ///<
UINT32 SpecialCycleEn:1 ; ///<
UINT32 MemWriteInvalidateEn:1 ; ///<
UINT32 PalSnoopEn:1 ; ///<
UINT32 ParityErrorEn:1 ; ///<
UINT32 Reserved_7_7:1 ; ///<
UINT32 SerrEn:1 ; ///<
UINT32 FastB2BEn:1 ; ///<
UINT32 Reserved_19_10:10; ///<
UINT32 CapList:1 ; ///<
UINT32 PCI66En:1 ; ///<
UINT32 Reserved_22_22:1 ; ///<
UINT32 FastBackCapable:1 ; ///<
UINT32 Reserved_24_24:1 ; ///<
UINT32 DevselTiming:2 ; ///<
UINT32 SignalTargetAbort:1 ; ///<
UINT32 ReceivedTargetAbort:1 ; ///<
UINT32 ReceivedMasterAbort:1 ; ///<
UINT32 SignaledSystemError:1 ; ///<
UINT32 ParityErrorDetected:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x04_STRUCT;
// **** D0F0x08 Register Definition ****
// Address
#define D0F0x08_ADDRESS 0x8
// Type
#define D0F0x08_TYPE TYPE_D0F0
// Field Data
#define D0F0x08_RevID_OFFSET 0
#define D0F0x08_RevID_WIDTH 8
#define D0F0x08_RevID_MASK 0xff
#define D0F0x08_ClassCode_OFFSET 8
#define D0F0x08_ClassCode_WIDTH 24
#define D0F0x08_ClassCode_MASK 0xffffff00
/// D0F0x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x08_STRUCT;
// **** D0F0x0C Register Definition ****
// Address
#define D0F0x0C_ADDRESS 0xc
// Type
#define D0F0x0C_TYPE TYPE_D0F0
// Field Data
#define D0F0x0C_CacheLineSize_OFFSET 0
#define D0F0x0C_CacheLineSize_WIDTH 8
#define D0F0x0C_CacheLineSize_MASK 0xff
#define D0F0x0C_LatencyTimer_OFFSET 8
#define D0F0x0C_LatencyTimer_WIDTH 8
#define D0F0x0C_LatencyTimer_MASK 0xff00
#define D0F0x0C_HeaderTypeReg_OFFSET 16
#define D0F0x0C_HeaderTypeReg_WIDTH 8
#define D0F0x0C_HeaderTypeReg_MASK 0xff0000
#define D0F0x0C_BIST_OFFSET 24
#define D0F0x0C_BIST_WIDTH 8
#define D0F0x0C_BIST_MASK 0xff000000
/// D0F0x0C
typedef union {
struct { ///<
UINT32 CacheLineSize:8 ; ///<
UINT32 LatencyTimer:8 ; ///<
UINT32 HeaderTypeReg:8 ; ///<
UINT32 BIST:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x0C_STRUCT;
// **** D0F0x2C Register Definition ****
// Address
#define D0F0x2C_ADDRESS 0x2c
// Type
#define D0F0x2C_TYPE TYPE_D0F0
// Field Data
#define D0F0x2C_SubsystemVendorID_OFFSET 0
#define D0F0x2C_SubsystemVendorID_WIDTH 16
#define D0F0x2C_SubsystemVendorID_MASK 0xffff
#define D0F0x2C_SubsystemID_OFFSET 16
#define D0F0x2C_SubsystemID_WIDTH 16
#define D0F0x2C_SubsystemID_MASK 0xffff0000
/// D0F0x2C
typedef union {
struct { ///<
UINT32 SubsystemVendorID:16; ///<
UINT32 SubsystemID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x2C_STRUCT;
// **** D0F0x34 Register Definition ****
// Address
#define D0F0x34_ADDRESS 0x34
// Type
#define D0F0x34_TYPE TYPE_D0F0
// Field Data
#define D0F0x34_CapPtr_OFFSET 0
#define D0F0x34_CapPtr_WIDTH 8
#define D0F0x34_CapPtr_MASK 0xff
#define D0F0x34_Reserved_31_8_OFFSET 8
#define D0F0x34_Reserved_31_8_WIDTH 24
#define D0F0x34_Reserved_31_8_MASK 0xffffff00
/// D0F0x34
typedef union {
struct { ///<
UINT32 CapPtr:8 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x34_STRUCT;
// **** D0F0x4C Register Definition ****
// Address
#define D0F0x4C_ADDRESS 0x4c
// Type
#define D0F0x4C_TYPE TYPE_D0F0
// Field Data
#define D0F0x4C_Function1Enable_OFFSET 0
#define D0F0x4C_Function1Enable_WIDTH 1
#define D0F0x4C_Function1Enable_MASK 0x1
#define D0F0x4C_ApicEnable_OFFSET 1
#define D0F0x4C_ApicEnable_WIDTH 1
#define D0F0x4C_ApicEnable_MASK 0x2
#define D0F0x4C_Reserved_2_2_OFFSET 2
#define D0F0x4C_Reserved_2_2_WIDTH 1
#define D0F0x4C_Reserved_2_2_MASK 0x4
#define D0F0x4C_Cf8Dis_OFFSET 3
#define D0F0x4C_Cf8Dis_WIDTH 1
#define D0F0x4C_Cf8Dis_MASK 0x8
#define D0F0x4C_PMEDis_OFFSET 4
#define D0F0x4C_PMEDis_WIDTH 1
#define D0F0x4C_PMEDis_MASK 0x10
#define D0F0x4C_SerrDis_OFFSET 5
#define D0F0x4C_SerrDis_WIDTH 1
#define D0F0x4C_SerrDis_MASK 0x20
#define D0F0x4C_Reserved_10_6_OFFSET 6
#define D0F0x4C_Reserved_10_6_WIDTH 5
#define D0F0x4C_Reserved_10_6_MASK 0x7c0
#define D0F0x4C_CRS_OFFSET 11
#define D0F0x4C_CRS_WIDTH 1
#define D0F0x4C_CRS_MASK 0x800
#define D0F0x4C_CfgRdTime_OFFSET 12
#define D0F0x4C_CfgRdTime_WIDTH 3
#define D0F0x4C_CfgRdTime_MASK 0x7000
#define D0F0x4C_Reserved_22_15_OFFSET 15
#define D0F0x4C_Reserved_22_15_WIDTH 8
#define D0F0x4C_Reserved_22_15_MASK 0x7f8000
#define D0F0x4C_MMIOEnable_OFFSET 23
#define D0F0x4C_MMIOEnable_WIDTH 1
#define D0F0x4C_MMIOEnable_MASK 0x800000
#define D0F0x4C_Reserved_25_24_OFFSET 24
#define D0F0x4C_Reserved_25_24_WIDTH 2
#define D0F0x4C_Reserved_25_24_MASK 0x3000000
#define D0F0x4C_HPDis_OFFSET 26
#define D0F0x4C_HPDis_WIDTH 1
#define D0F0x4C_HPDis_MASK 0x4000000
#define D0F0x4C_Reserved_31_27_OFFSET 27
#define D0F0x4C_Reserved_31_27_WIDTH 5
#define D0F0x4C_Reserved_31_27_MASK 0xf8000000
/// D0F0x4C
typedef union {
struct { ///<
UINT32 Function1Enable:1 ; ///<
UINT32 ApicEnable:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 Cf8Dis:1 ; ///<
UINT32 PMEDis:1 ; ///<
UINT32 SerrDis:1 ; ///<
UINT32 Reserved_10_6:5 ; ///<
UINT32 CRS:1 ; ///<
UINT32 CfgRdTime:3 ; ///<
UINT32 Reserved_22_15:8 ; ///<
UINT32 MMIOEnable:1 ; ///<
UINT32 Reserved_25_24:2 ; ///<
UINT32 HPDis:1 ; ///<
UINT32 Reserved_31_27:5 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x4C_STRUCT;
// **** D0F0x60 Register Definition ****
// Address
#define D0F0x60_ADDRESS 0x60
// Type
#define D0F0x60_TYPE TYPE_D0F0
// Field Data
#define D0F0x60_MiscIndAddr_OFFSET 0
#define D0F0x60_MiscIndAddr_WIDTH 7
#define D0F0x60_MiscIndAddr_MASK 0x7f
#define D0F0x60_MiscIndWrEn_OFFSET 7
#define D0F0x60_MiscIndWrEn_WIDTH 1
#define D0F0x60_MiscIndWrEn_MASK 0x80
#define D0F0x60_Reserved_31_8_OFFSET 8
#define D0F0x60_Reserved_31_8_WIDTH 24
#define D0F0x60_Reserved_31_8_MASK 0xffffff00
/// D0F0x60
typedef union {
struct { ///<
UINT32 MiscIndAddr:7 ; ///<
UINT32 MiscIndWrEn:1 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x60_STRUCT;
// **** D0F0x64 Register Definition ****
// Address
#define D0F0x64_ADDRESS 0x64
// Type
#define D0F0x64_TYPE TYPE_D0F0
// Field Data
#define D0F0x64_MiscIndData_OFFSET 0
#define D0F0x64_MiscIndData_WIDTH 32
#define D0F0x64_MiscIndData_MASK 0xffffffff
/// D0F0x64
typedef union {
struct { ///<
UINT32 MiscIndData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x64_STRUCT;
/// D0F0x78
typedef union {
struct { ///<
UINT32 Scratch:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x78_STRUCT;
// **** D0F0x7C Register Definition ****
// Address
#define D0F0x7C_ADDRESS 0x7c
// Type
#define D0F0x7C_TYPE TYPE_D0F0
// Field Data
#define D0F0x7C_ForceIntGFXDisable_OFFSET 0
#define D0F0x7C_ForceIntGFXDisable_WIDTH 1
#define D0F0x7C_ForceIntGFXDisable_MASK 0x1
#define D0F0x7C_Reserved_31_1_OFFSET 1
#define D0F0x7C_Reserved_31_1_WIDTH 31
#define D0F0x7C_Reserved_31_1_MASK 0xfffffffe
/// D0F0x7C
typedef union {
struct { ///<
UINT32 ForceIntGFXDisable:1 ; ///<
UINT32 Reserved_31_1:31; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x7C_STRUCT;
// **** D0F0x84 Register Definition ****
// Address
#define D0F0x84_ADDRESS 0x84
// Type
#define D0F0x84_TYPE TYPE_D0F0
// Field Data
#define D0F0x84_Reserved_3_0_OFFSET 0
#define D0F0x84_Reserved_3_0_WIDTH 4
#define D0F0x84_Reserved_3_0_MASK 0xf
#define D0F0x84_Ev6Mode_OFFSET 4
#define D0F0x84_Ev6Mode_WIDTH 1
#define D0F0x84_Ev6Mode_MASK 0x10
#define D0F0x84_Reserved_7_5_OFFSET 5
#define D0F0x84_Reserved_7_5_WIDTH 3
#define D0F0x84_Reserved_7_5_MASK 0xe0
#define D0F0x84_PmeMode_OFFSET 8
#define D0F0x84_PmeMode_WIDTH 1
#define D0F0x84_PmeMode_MASK 0x100
#define D0F0x84_PmeTurnOff_OFFSET 9
#define D0F0x84_PmeTurnOff_WIDTH 1
#define D0F0x84_PmeTurnOff_MASK 0x200
#define D0F0x84_Reserved_31_10_OFFSET 10
#define D0F0x84_Reserved_31_10_WIDTH 22
#define D0F0x84_Reserved_31_10_MASK 0xfffffc00
/// D0F0x84
typedef union {
struct { ///<
UINT32 Reserved_3_0:4 ; ///<
UINT32 Ev6Mode:1 ; ///<
UINT32 Reserved_7_5:3 ; ///<
UINT32 PmeMode:1 ; ///<
UINT32 PmeTurnOff:1 ; ///<
UINT32 Reserved_31_10:22; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x84_STRUCT;
// **** D0F0x90 Register Definition ****
// Address
#define D0F0x90_ADDRESS 0x90
// Type
#define D0F0x90_TYPE TYPE_D0F0
// Field Data
#define D0F0x90_Reserved_22_0_OFFSET 0
#define D0F0x90_Reserved_22_0_WIDTH 23
#define D0F0x90_Reserved_22_0_MASK 0x7fffff
#define D0F0x90_TopOfDram_OFFSET 23
#define D0F0x90_TopOfDram_WIDTH 9
#define D0F0x90_TopOfDram_MASK 0xff800000
/// D0F0x90
typedef union {
struct { ///<
UINT32 Reserved_22_0:23; ///<
UINT32 TopOfDram:9 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x90_STRUCT;
// **** D0F0x94 Register Definition ****
// Address
#define D0F0x94_ADDRESS 0x94
// Type
#define D0F0x94_TYPE TYPE_D0F0
// Field Data
#define D0F0x94_OrbIndAddr_OFFSET 0
#define D0F0x94_OrbIndAddr_WIDTH 7
#define D0F0x94_OrbIndAddr_MASK 0x7f
#define D0F0x94_Reserved_7_7_OFFSET 7
#define D0F0x94_Reserved_7_7_WIDTH 1
#define D0F0x94_Reserved_7_7_MASK 0x80
#define D0F0x94_OrbIndWrEn_OFFSET 8
#define D0F0x94_OrbIndWrEn_WIDTH 1
#define D0F0x94_OrbIndWrEn_MASK 0x100
#define D0F0x94_Reserved_31_9_OFFSET 9
#define D0F0x94_Reserved_31_9_WIDTH 23
#define D0F0x94_Reserved_31_9_MASK 0xfffffe00
/// D0F0x94
typedef union {
struct { ///<
UINT32 OrbIndAddr:7 ; ///<
UINT32 Reserved_7_7:1 ; ///<
UINT32 OrbIndWrEn:1 ; ///<
UINT32 Reserved_31_9:23; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x94_STRUCT;
// **** D0F0x98 Register Definition ****
// Address
#define D0F0x98_ADDRESS 0x98
// Type
#define D0F0x98_TYPE TYPE_D0F0
// Field Data
#define D0F0x98_OrbIndData_OFFSET 0
#define D0F0x98_OrbIndData_WIDTH 32
#define D0F0x98_OrbIndData_MASK 0xffffffff
/// D0F0x98
typedef union {
struct { ///<
UINT32 OrbIndData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0x98_STRUCT;
// **** D0F0xE0 Register Definition ****
// Address
#define D0F0xE0_ADDRESS 0xe0
// Type
#define D0F0xE0_TYPE TYPE_D0F0
// Field Data
#define D0F0xE0_PcieIndxAddr_OFFSET 0
#define D0F0xE0_PcieIndxAddr_WIDTH 16
#define D0F0xE0_PcieIndxAddr_MASK 0xffff
#define D0F0xE0_FrameType_OFFSET 16
#define D0F0xE0_FrameType_WIDTH 8
#define D0F0xE0_FrameType_MASK 0xff0000
#define D0F0xE0_BlockSelect_OFFSET 24
#define D0F0xE0_BlockSelect_WIDTH 8
#define D0F0xE0_BlockSelect_MASK 0xff000000
/// D0F0xE0
typedef union {
struct { ///<
UINT32 PcieIndxAddr:16; ///<
UINT32 FrameType:8 ; ///<
UINT32 BlockSelect:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE0_STRUCT;
// **** D0F0xE4 Register Definition ****
// Address
#define D0F0xE4_ADDRESS 0xe4
// Type
#define D0F0xE4_TYPE TYPE_D0F0
// Field Data
#define D0F0xE4_PcieIndxData_OFFSET 0
#define D0F0xE4_PcieIndxData_WIDTH 32
#define D0F0xE4_PcieIndxData_MASK 0xffffffff
/// D0F0xE4
typedef union {
struct { ///<
UINT32 PcieIndxData:32; ///<
} Field; ///<
UINT32 Value; ///<
} D0F0xE4_STRUCT;
// **** D18F1xF0 Register Definition ****
// Address
#define D18F1xF0_ADDRESS 0xf0
// Type
#define D18F1xF0_TYPE TYPE_D18F1
// Field Data
#define D18F1xF0_DramHoleValid_OFFSET 0
#define D18F1xF0_DramHoleValid_WIDTH 1
#define D18F1xF0_DramHoleValid_MASK 0x1
#define D18F1xF0_Reserved_6_1_OFFSET 1
#define D18F1xF0_Reserved_6_1_WIDTH 6
#define D18F1xF0_Reserved_6_1_MASK 0x7e
#define D18F1xF0_DramHoleOffset_31_23__OFFSET 7
#define D18F1xF0_DramHoleOffset_31_23__WIDTH 9
#define D18F1xF0_DramHoleOffset_31_23__MASK 0xff80
#define D18F1xF0_Reserved_23_16_OFFSET 16
#define D18F1xF0_Reserved_23_16_WIDTH 8
#define D18F1xF0_Reserved_23_16_MASK 0xff0000
#define D18F1xF0_DramHoleBase_31_24__OFFSET 24
#define D18F1xF0_DramHoleBase_31_24__WIDTH 8
#define D18F1xF0_DramHoleBase_31_24__MASK 0xff000000
/// D18F1xF0
typedef union {
struct { ///<
UINT32 DramHoleValid:1 ; ///<
UINT32 Reserved_6_1:6 ; ///<
UINT32 DramHoleOffset_31_23_:9 ; ///<
UINT32 Reserved_23_16:8 ; ///<
UINT32 DramHoleBase_31_24_:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F1xF0_STRUCT;
// **** D18F2x00 Register Definition ****
// Address
#define D18F2x00_ADDRESS 0x0
// Type
#define D18F2x00_TYPE TYPE_D18F2
// Field Data
#define D18F2x00_VendorID_OFFSET 0
#define D18F2x00_VendorID_WIDTH 16
#define D18F2x00_VendorID_MASK 0xffff
#define D18F2x00_DeviceID_OFFSET 16
#define D18F2x00_DeviceID_WIDTH 16
#define D18F2x00_DeviceID_MASK 0xffff0000
/// D18F2x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x00_STRUCT;
// **** D18F2x08 Register Definition ****
// Address
#define D18F2x08_ADDRESS 0x8
// Type
#define D18F2x08_TYPE TYPE_D18F2
// Field Data
#define D18F2x08_RevID_OFFSET 0
#define D18F2x08_RevID_WIDTH 8
#define D18F2x08_RevID_MASK 0xff
#define D18F2x08_ClassCode_OFFSET 8
#define D18F2x08_ClassCode_WIDTH 24
#define D18F2x08_ClassCode_MASK 0xffffff00
/// D18F2x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x08_STRUCT;
// **** D18F2x0C Register Definition ****
// Address
#define D18F2x0C_ADDRESS 0xc
// Type
#define D18F2x0C_TYPE TYPE_D18F2
// Field Data
#define D18F2x0C_HeaderTypeReg_OFFSET 0
#define D18F2x0C_HeaderTypeReg_WIDTH 32
#define D18F2x0C_HeaderTypeReg_MASK 0xffffffff
/// D18F2x0C
typedef union {
struct { ///<
UINT32 HeaderTypeReg:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x0C_STRUCT;
// **** D18F2x040 Register Definition ****
// Address
#define D18F2x040_ADDRESS 0x40
// Type
#define D18F2x040_TYPE TYPE_D18F2
// Field Data
#define D18F2x040_CSEnable_OFFSET 0
#define D18F2x040_CSEnable_WIDTH 1
#define D18F2x040_CSEnable_MASK 0x1
#define D18F2x040_Reserved_1_1_OFFSET 1
#define D18F2x040_Reserved_1_1_WIDTH 1
#define D18F2x040_Reserved_1_1_MASK 0x2
#define D18F2x040_TestFail_OFFSET 2
#define D18F2x040_TestFail_WIDTH 1
#define D18F2x040_TestFail_MASK 0x4
#define D18F2x040_OnDimmMirror_OFFSET 3
#define D18F2x040_OnDimmMirror_WIDTH 1
#define D18F2x040_OnDimmMirror_MASK 0x8
#define D18F2x040_Reserved_4_4_OFFSET 4
#define D18F2x040_Reserved_4_4_WIDTH 1
#define D18F2x040_Reserved_4_4_MASK 0x10
#define D18F2x040_Reserved_31_29_OFFSET 29
#define D18F2x040_Reserved_31_29_WIDTH 3
#define D18F2x040_Reserved_31_29_MASK 0xe0000000
/// D18F2x040
typedef union {
struct { ///<
UINT32 CSEnable:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 TestFail:1 ; ///<
UINT32 OnDimmMirror:1 ; ///<
UINT32 Reserved_4_4:1 ; ///<
UINT32 :9 ; ///<
UINT32 Reserved_18_14:5 ; ///<
UINT32 :10; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x040_STRUCT;
// **** D18F2x044 Register Definition ****
// Address
#define D18F2x044_ADDRESS 0x44
// Type
#define D18F2x044_TYPE TYPE_D18F2
// Field Data
#define D18F2x044_CSEnable_OFFSET 0
#define D18F2x044_CSEnable_WIDTH 1
#define D18F2x044_CSEnable_MASK 0x1
#define D18F2x044_Reserved_1_1_OFFSET 1
#define D18F2x044_Reserved_1_1_WIDTH 1
#define D18F2x044_Reserved_1_1_MASK 0x2
#define D18F2x044_TestFail_OFFSET 2
#define D18F2x044_TestFail_WIDTH 1
#define D18F2x044_TestFail_MASK 0x4
#define D18F2x044_OnDimmMirror_OFFSET 3
#define D18F2x044_OnDimmMirror_WIDTH 1
#define D18F2x044_OnDimmMirror_MASK 0x8
#define D18F2x044_Reserved_4_4_OFFSET 4
#define D18F2x044_Reserved_4_4_WIDTH 1
#define D18F2x044_Reserved_4_4_MASK 0x10
#define D18F2x044_Reserved_31_29_OFFSET 29
#define D18F2x044_Reserved_31_29_WIDTH 3
#define D18F2x044_Reserved_31_29_MASK 0xe0000000
/// D18F2x044
typedef union {
struct { ///<
UINT32 CSEnable:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 TestFail:1 ; ///<
UINT32 OnDimmMirror:1 ; ///<
UINT32 Reserved_4_4:1 ; ///<
UINT32 :9 ; ///<
UINT32 Reserved_18_14:5 ; ///<
UINT32 :10; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x044_STRUCT;
// **** D18F2x048 Register Definition ****
// Address
#define D18F2x048_ADDRESS 0x48
// Type
#define D18F2x048_TYPE TYPE_D18F2
// Field Data
#define D18F2x048_CSEnable_OFFSET 0
#define D18F2x048_CSEnable_WIDTH 1
#define D18F2x048_CSEnable_MASK 0x1
#define D18F2x048_Reserved_1_1_OFFSET 1
#define D18F2x048_Reserved_1_1_WIDTH 1
#define D18F2x048_Reserved_1_1_MASK 0x2
#define D18F2x048_TestFail_OFFSET 2
#define D18F2x048_TestFail_WIDTH 1
#define D18F2x048_TestFail_MASK 0x4
#define D18F2x048_OnDimmMirror_OFFSET 3
#define D18F2x048_OnDimmMirror_WIDTH 1
#define D18F2x048_OnDimmMirror_MASK 0x8
#define D18F2x048_Reserved_4_4_OFFSET 4
#define D18F2x048_Reserved_4_4_WIDTH 1
#define D18F2x048_Reserved_4_4_MASK 0x10
#define D18F2x048_Reserved_31_29_OFFSET 29
#define D18F2x048_Reserved_31_29_WIDTH 3
#define D18F2x048_Reserved_31_29_MASK 0xe0000000
/// D18F2x048
typedef union {
struct { ///<
UINT32 CSEnable:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 TestFail:1 ; ///<
UINT32 OnDimmMirror:1 ; ///<
UINT32 Reserved_4_4:1 ; ///<
UINT32 :9 ; ///<
UINT32 Reserved_18_14:5 ; ///<
UINT32 :10; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x048_STRUCT;
// **** D18F2x04C Register Definition ****
// Address
#define D18F2x04C_ADDRESS 0x4c
// Type
#define D18F2x04C_TYPE TYPE_D18F2
// Field Data
#define D18F2x04C_CSEnable_OFFSET 0
#define D18F2x04C_CSEnable_WIDTH 1
#define D18F2x04C_CSEnable_MASK 0x1
#define D18F2x04C_Reserved_1_1_OFFSET 1
#define D18F2x04C_Reserved_1_1_WIDTH 1
#define D18F2x04C_Reserved_1_1_MASK 0x2
#define D18F2x04C_TestFail_OFFSET 2
#define D18F2x04C_TestFail_WIDTH 1
#define D18F2x04C_TestFail_MASK 0x4
#define D18F2x04C_OnDimmMirror_OFFSET 3
#define D18F2x04C_OnDimmMirror_WIDTH 1
#define D18F2x04C_OnDimmMirror_MASK 0x8
#define D18F2x04C_Reserved_4_4_OFFSET 4
#define D18F2x04C_Reserved_4_4_WIDTH 1
#define D18F2x04C_Reserved_4_4_MASK 0x10
#define D18F2x04C_Reserved_31_29_OFFSET 29
#define D18F2x04C_Reserved_31_29_WIDTH 3
#define D18F2x04C_Reserved_31_29_MASK 0xe0000000
/// D18F2x04C
typedef union {
struct { ///<
UINT32 CSEnable:1 ; ///<
UINT32 Reserved_1_1:1 ; ///<
UINT32 TestFail:1 ; ///<
UINT32 OnDimmMirror:1 ; ///<
UINT32 Reserved_4_4:1 ; ///<
UINT32 :9 ; ///<
UINT32 Reserved_18_14:5 ; ///<
UINT32 :10; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x04C_STRUCT;
// **** D18F2x060 Register Definition ****
// Address
#define D18F2x060_ADDRESS 0x60
// Type
#define D18F2x060_TYPE TYPE_D18F2
// Field Data
#define D18F2x060_Reserved_4_0_OFFSET 0
#define D18F2x060_Reserved_4_0_WIDTH 5
#define D18F2x060_Reserved_4_0_MASK 0x1f
#define D18F2x060_Reserved_31_29_OFFSET 29
#define D18F2x060_Reserved_31_29_WIDTH 3
#define D18F2x060_Reserved_31_29_MASK 0xe0000000
/// D18F2x060
typedef union {
struct { ///<
UINT32 Reserved_4_0:5 ; ///<
UINT32 :9 ; ///<
UINT32 Reserved_18_14:5 ; ///<
UINT32 :10; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x060_STRUCT;
// **** D18F2x064 Register Definition ****
// Address
#define D18F2x064_ADDRESS 0x64
// Type
#define D18F2x064_TYPE TYPE_D18F2
// Field Data
#define D18F2x064_Reserved_4_0_OFFSET 0
#define D18F2x064_Reserved_4_0_WIDTH 5
#define D18F2x064_Reserved_4_0_MASK 0x1f
#define D18F2x064_Reserved_31_29_OFFSET 29
#define D18F2x064_Reserved_31_29_WIDTH 3
#define D18F2x064_Reserved_31_29_MASK 0xe0000000
/// D18F2x064
typedef union {
struct { ///<
UINT32 Reserved_4_0:5 ; ///<
UINT32 :9 ; ///<
UINT32 Reserved_18_14:5 ; ///<
UINT32 :10; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x064_STRUCT;
// **** D18F2x078 Register Definition ****
// Address
#define D18F2x078_ADDRESS 0x78
// Type
#define D18F2x078_TYPE TYPE_D18F2
// Field Data
#define D18F2x078_Reserved_14_14_OFFSET 14
#define D18F2x078_Reserved_14_14_WIDTH 1
#define D18F2x078_Reserved_14_14_MASK 0x4000
#define D18F2x078_Reserved_15_15_OFFSET 15
#define D18F2x078_Reserved_15_15_WIDTH 1
#define D18F2x078_Reserved_15_15_MASK 0x8000
#define D18F2x078_Reserved_16_16_OFFSET 16
#define D18F2x078_Reserved_16_16_WIDTH 1
#define D18F2x078_Reserved_16_16_MASK 0x10000
#define D18F2x078_AddrCmdTriEn_OFFSET 17
#define D18F2x078_AddrCmdTriEn_WIDTH 1
#define D18F2x078_AddrCmdTriEn_MASK 0x20000
#define D18F2x078_Reserved_18_18_OFFSET 18
#define D18F2x078_Reserved_18_18_WIDTH 1
#define D18F2x078_Reserved_18_18_MASK 0x40000
#define D18F2x078_Reserved_19_19_OFFSET 19
#define D18F2x078_Reserved_19_19_WIDTH 1
#define D18F2x078_Reserved_19_19_MASK 0x80000
/// D18F2x078
typedef union {
struct { ///<
UINT32 :4 ; ///<
UINT32 :2 ; ///<
UINT32 :1 ; ///<
UINT32 :1 ; ///<
UINT32 :2 ; ///<
UINT32 :2 ; ///<
UINT32 :2 ; ///<
UINT32 Reserved_14_14:1 ; ///<
UINT32 Reserved_15_15:1 ; ///<
UINT32 Reserved_16_16:1 ; ///<
UINT32 AddrCmdTriEn:1 ; ///<
UINT32 Reserved_18_18:1 ; ///<
UINT32 Reserved_19_19:1 ; ///<
UINT32 :1 ; ///<
UINT32 :1 ; ///<
UINT32 :10; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x078_STRUCT;
// **** D18F2x084 Register Definition ****
// Address
#define D18F2x084_ADDRESS 0x84
// Type
#define D18F2x084_TYPE TYPE_D18F2
// Field Data
#define D18F2x084_BurstCtrl_OFFSET 0
#define D18F2x084_BurstCtrl_WIDTH 2
#define D18F2x084_BurstCtrl_MASK 0x3
#define D18F2x084_Reserved_3_2_OFFSET 2
#define D18F2x084_Reserved_3_2_WIDTH 2
#define D18F2x084_Reserved_3_2_MASK 0xc
#define D18F2x084_Reserved_19_7_OFFSET 7
#define D18F2x084_Reserved_19_7_WIDTH 13
#define D18F2x084_Reserved_19_7_MASK 0xfff80
#define D18F2x084_PchgPDModeSel_OFFSET 23
#define D18F2x084_PchgPDModeSel_WIDTH 1
#define D18F2x084_PchgPDModeSel_MASK 0x800000
#define D18F2x084_Reserved_31_24_OFFSET 24
#define D18F2x084_Reserved_31_24_WIDTH 8
#define D18F2x084_Reserved_31_24_MASK 0xff000000
/// D18F2x084
typedef union {
struct { ///<
UINT32 BurstCtrl:2 ; ///<
UINT32 Reserved_3_2:2 ; ///<
UINT32 :3 ; ///<
UINT32 Reserved_19_7:13; ///<
UINT32 :3 ; ///<
UINT32 PchgPDModeSel:1 ; ///<
UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x084_STRUCT;
// **** D18F2x088 Register Definition ****
// Address
#define D18F2x088_ADDRESS 0x88
// Type
#define D18F2x088_TYPE TYPE_D18F2
// Field Data
#define D18F2x088_Reserved_23_4_OFFSET 4
#define D18F2x088_Reserved_23_4_WIDTH 20
#define D18F2x088_Reserved_23_4_MASK 0xfffff0
/// D18F2x088
typedef union {
struct { ///<
UINT32 :4 ; ///<
UINT32 Reserved_23_4:20; ///<
UINT32 :8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x088_STRUCT;
// **** D18F2x098 Register Definition ****
// Address
#define D18F2x098_ADDRESS 0x98
// Type
#define D18F2x098_TYPE TYPE_D18F2
// Field Data
#define D18F2x098_DctOffset_OFFSET 0
#define D18F2x098_DctOffset_WIDTH 30
#define D18F2x098_DctOffset_MASK 0x3fffffff
#define D18F2x098_DctAccessWrite_OFFSET 30
#define D18F2x098_DctAccessWrite_WIDTH 1
#define D18F2x098_DctAccessWrite_MASK 0x40000000
#define D18F2x098_Reserved_31_31_OFFSET 31
#define D18F2x098_Reserved_31_31_WIDTH 1
#define D18F2x098_Reserved_31_31_MASK 0x80000000
/// D18F2x098
typedef union {
struct { ///<
UINT32 DctOffset:30; ///<
UINT32 DctAccessWrite:1 ; ///<
UINT32 Reserved_31_31:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x098_STRUCT;
// **** D18F2x09C Register Definition ****
// Address
#define D18F2x09C_ADDRESS 0x9c
// Type
#define D18F2x09C_TYPE TYPE_D18F2
// Field Data
#define D18F2x09C_DctDataPort_OFFSET 0
#define D18F2x09C_DctDataPort_WIDTH 32
#define D18F2x09C_DctDataPort_MASK 0xffffffff
/// D18F2x09C
typedef union {
struct { ///<
UINT32 DctDataPort:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x09C_STRUCT;
// **** D18F2xA4 Register Definition ****
// Address
#define D18F2xA4_ADDRESS 0xa4
// Type
#define D18F2xA4_TYPE TYPE_D18F2
// Field Data
#define D18F2xA4_DoubleTrefRateEn_OFFSET 0
#define D18F2xA4_DoubleTrefRateEn_WIDTH 1
// **** D18F2xAC Register Definition ****
// Address
#define D18F2xAC_ADDRESS 0xac
// Type
#define D18F2xAC_TYPE TYPE_D18F2
// Field Data
#define D18F2xAC_Reserved_31_1_OFFSET 1
#define D18F2xAC_Reserved_31_1_WIDTH 31
#define D18F2xAC_Reserved_31_1_MASK 0xfffffffe
/// D18F2xAC
typedef union {
struct { ///<
UINT32 MemTempHot:1 ; ///<
UINT32 Reserved_31_1:31; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2xAC_STRUCT;
// **** D18F2x114 Register Definition ****
// Address
#define D18F2x114_ADDRESS 0x114
// Type
#define D18F2x114_TYPE TYPE_D18F2
// Field Data
#define D18F2x114_Reserved_8_0_OFFSET 0
#define D18F2x114_Reserved_8_0_WIDTH 9
#define D18F2x114_Reserved_8_0_MASK 0x1ff
#define D18F2x114_DctSelIntLvAddr_2__OFFSET 9
#define D18F2x114_DctSelIntLvAddr_2__WIDTH 1
#define D18F2x114_DctSelIntLvAddr_2__MASK 0x200
/// D18F2x114
typedef union {
struct { ///<
UINT32 Reserved_8_0:9 ; ///<
UINT32 DctSelIntLvAddr_2_:1 ; ///<
UINT32 :14; ///<
UINT32 :8 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F2x114_STRUCT;
// **** D18F3x00 Register Definition ****
// Address
#define D18F3x00_ADDRESS 0x0
// Type
#define D18F3x00_TYPE TYPE_D18F3
// Field Data
#define D18F3x00_VendorID_OFFSET 0
#define D18F3x00_VendorID_WIDTH 16
#define D18F3x00_VendorID_MASK 0xffff
#define D18F3x00_DeviceID_OFFSET 16
#define D18F3x00_DeviceID_WIDTH 16
#define D18F3x00_DeviceID_MASK 0xffff0000
/// D18F3x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x00_STRUCT;
// **** D18F3x04 Register Definition ****
// Address
#define D18F3x04_ADDRESS 0x4
// Type
#define D18F3x04_TYPE TYPE_D18F3
// Field Data
#define D18F3x04_Command_OFFSET 0
#define D18F3x04_Command_WIDTH 16
#define D18F3x04_Command_MASK 0xffff
#define D18F3x04_Status_OFFSET 16
#define D18F3x04_Status_WIDTH 16
#define D18F3x04_Status_MASK 0xffff0000
/// D18F3x04
typedef union {
struct { ///<
UINT32 Command:16; ///<
UINT32 Status:16; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x04_STRUCT;
// **** D18F3x08 Register Definition ****
// Address
#define D18F3x08_ADDRESS 0x8
// Type
#define D18F3x08_TYPE TYPE_D18F3
// Field Data
#define D18F3x08_RevID_OFFSET 0
#define D18F3x08_RevID_WIDTH 8
#define D18F3x08_RevID_MASK 0xff
#define D18F3x08_ClassCode_OFFSET 8
#define D18F3x08_ClassCode_WIDTH 24
#define D18F3x08_ClassCode_MASK 0xffffff00
/// D18F3x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x08_STRUCT;
// **** D18F3x0C Register Definition ****
// Address
#define D18F3x0C_ADDRESS 0xc
// Type
#define D18F3x0C_TYPE TYPE_D18F3
// Field Data
#define D18F3x0C_HeaderTypeReg_OFFSET 0
#define D18F3x0C_HeaderTypeReg_WIDTH 32
#define D18F3x0C_HeaderTypeReg_MASK 0xffffffff
/// D18F3x0C
typedef union {
struct { ///<
UINT32 HeaderTypeReg:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x0C_STRUCT;
// **** D18F3x34 Register Definition ****
// Address
#define D18F3x34_ADDRESS 0x34
// Type
#define D18F3x34_TYPE TYPE_D18F3
// Field Data
#define D18F3x34_CapPtr_OFFSET 0
#define D18F3x34_CapPtr_WIDTH 8
#define D18F3x34_CapPtr_MASK 0xff
#define D18F3x34_Reserved_31_8_OFFSET 8
#define D18F3x34_Reserved_31_8_WIDTH 24
#define D18F3x34_Reserved_31_8_MASK 0xffffff00
/// D18F3x34
typedef union {
struct { ///<
UINT32 CapPtr:8 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x34_STRUCT;
// **** D18F3x48 Register Definition ****
// Address
#define D18F3x48_ADDRESS 0x48
// Type
#define D18F3x48_TYPE TYPE_D18F3
// Field Data
#define D18F3x48_ErrorCode_OFFSET 0
#define D18F3x48_ErrorCode_WIDTH 16
#define D18F3x48_ErrorCode_MASK 0xffff
#define D18F3x48_ErrorCodeExt_OFFSET 16
#define D18F3x48_ErrorCodeExt_WIDTH 5
#define D18F3x48_ErrorCodeExt_MASK 0x1f0000
#define D18F3x48_Reserved_31_21_OFFSET 21
#define D18F3x48_Reserved_31_21_WIDTH 11
#define D18F3x48_Reserved_31_21_MASK 0xffe00000
/// D18F3x48
typedef union {
struct { ///<
UINT32 ErrorCode:16; ///<
UINT32 ErrorCodeExt:5 ; ///<
UINT32 Reserved_31_21:11; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x48_STRUCT;
// **** D18F3x64 Register Definition ****
// Address
#define D18F3x64_ADDRESS 0x64
// Type
#define D18F3x64_TYPE TYPE_D18F3
// Field Data
#define D18F3x64_HtcEn_OFFSET 0
#define D18F3x64_HtcEn_WIDTH 1
#define D18F3x64_HtcEn_MASK 0x1
#define D18F3x64_Reserved_3_1_OFFSET 1
#define D18F3x64_Reserved_3_1_WIDTH 3
#define D18F3x64_Reserved_3_1_MASK 0xe
#define D18F3x64_HtcAct_OFFSET 4
#define D18F3x64_HtcAct_WIDTH 1
#define D18F3x64_HtcAct_MASK 0x10
#define D18F3x64_HtcActSts_OFFSET 5
#define D18F3x64_HtcActSts_WIDTH 1
#define D18F3x64_HtcActSts_MASK 0x20
#define D18F3x64_PslApicHiEn_OFFSET 6
#define D18F3x64_PslApicHiEn_WIDTH 1
#define D18F3x64_PslApicHiEn_MASK 0x40
#define D18F3x64_PslApicLoEn_OFFSET 7
#define D18F3x64_PslApicLoEn_WIDTH 1
#define D18F3x64_PslApicLoEn_MASK 0x80
#define D18F3x64_Reserved_15_8_OFFSET 8
#define D18F3x64_Reserved_15_8_WIDTH 8
#define D18F3x64_Reserved_15_8_MASK 0xff00
#define D18F3x64_HtcTmpLmt_OFFSET 16
#define D18F3x64_HtcTmpLmt_WIDTH 7
#define D18F3x64_HtcTmpLmt_MASK 0x7f0000
#define D18F3x64_HtcSlewSel_OFFSET 23
#define D18F3x64_HtcSlewSel_WIDTH 1
#define D18F3x64_HtcSlewSel_MASK 0x800000
#define D18F3x64_HtcHystLmt_OFFSET 24
#define D18F3x64_HtcHystLmt_WIDTH 4
#define D18F3x64_HtcHystLmt_MASK 0xf000000
#define D18F3x64_HtcPstateLimit_OFFSET 28
#define D18F3x64_HtcPstateLimit_WIDTH 3
#define D18F3x64_HtcPstateLimit_MASK 0x70000000
/// D18F3x64
typedef union {
struct { ///<
UINT32 HtcEn:1 ; ///<
UINT32 Reserved_3_1:3 ; ///<
UINT32 HtcAct:1 ; ///<
UINT32 HtcActSts:1 ; ///<
UINT32 PslApicHiEn:1 ; ///<
UINT32 PslApicLoEn:1 ; ///<
UINT32 Reserved_15_8:8 ; ///<
UINT32 HtcTmpLmt:7 ; ///<
UINT32 HtcSlewSel:1 ; ///<
UINT32 HtcHystLmt:4 ; ///<
UINT32 HtcPstateLimit:3 ; ///<
UINT32 :1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x64_STRUCT;
// **** D18F3x88 Register Definition ****
// Address
#define D18F3x88_ADDRESS 0x88
// Type
#define D18F3x88_TYPE TYPE_D18F3
// Field Data
#define D18F3x88_Reserved_31_0_OFFSET 0
#define D18F3x88_Reserved_31_0_WIDTH 32
#define D18F3x88_Reserved_31_0_MASK 0xffffffff
/// D18F3x88
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x88_STRUCT;
// **** D18F3xE4 Register Definition ****
// Address
#define D18F3xE4_ADDRESS 0xe4
// Type
#define D18F3xE4_TYPE TYPE_D18F3
// Field Data
#define D18F3xE4_Reserved_0_0_OFFSET 0
#define D18F3xE4_Reserved_0_0_WIDTH 1
#define D18F3xE4_Reserved_0_0_MASK 0x1
#define D18F3xE4_Thermtp_OFFSET 1
#define D18F3xE4_Thermtp_WIDTH 1
#define D18F3xE4_Thermtp_MASK 0x2
#define D18F3xE4_Reserved_2_2_OFFSET 2
#define D18F3xE4_Reserved_2_2_WIDTH 1
#define D18F3xE4_Reserved_2_2_MASK 0x4
#define D18F3xE4_ThermtpSense_OFFSET 3
#define D18F3xE4_ThermtpSense_WIDTH 1
#define D18F3xE4_ThermtpSense_MASK 0x8
#define D18F3xE4_Reserved_4_4_OFFSET 4
#define D18F3xE4_Reserved_4_4_WIDTH 1
#define D18F3xE4_Reserved_4_4_MASK 0x10
#define D18F3xE4_ThermtpEn_OFFSET 5
#define D18F3xE4_ThermtpEn_WIDTH 1
#define D18F3xE4_ThermtpEn_MASK 0x20
#define D18F3xE4_Reserved_7_6_OFFSET 6
#define D18F3xE4_Reserved_7_6_WIDTH 2
#define D18F3xE4_Reserved_7_6_MASK 0xc0
#define D18F3xE4_Reserved_30_8_OFFSET 8
#define D18F3xE4_Reserved_30_8_WIDTH 23
#define D18F3xE4_Reserved_30_8_MASK 0x7fffff00
#define D18F3xE4_SwThermtp_OFFSET 31
#define D18F3xE4_SwThermtp_WIDTH 1
#define D18F3xE4_SwThermtp_MASK 0x80000000
/// D18F3xE4
typedef union {
struct { ///<
UINT32 Reserved_0_0:1 ; ///<
UINT32 Thermtp:1 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 ThermtpSense:1 ; ///<
UINT32 Reserved_4_4:1 ; ///<
UINT32 ThermtpEn:1 ; ///<
UINT32 Reserved_7_6:2 ; ///<
UINT32 Reserved_30_8:23; ///<
UINT32 SwThermtp:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3xE4_STRUCT;
// **** D18F3xF0 Register Definition ****
// Address
#define D18F3xF0_ADDRESS 0xf0
// Type
#define D18F3xF0_TYPE TYPE_D18F3
// Field Data
#define D18F3xF0_Reserved_31_0_OFFSET 0
#define D18F3xF0_Reserved_31_0_WIDTH 32
#define D18F3xF0_Reserved_31_0_MASK 0xffffffff
/// D18F3xF0
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3xF0_STRUCT;
// **** D18F3xF4 Register Definition ****
// Address
#define D18F3xF4_ADDRESS 0xf4
// Type
#define D18F3xF4_TYPE TYPE_D18F3
// Field Data
#define D18F3xF4_Reserved_31_0_OFFSET 0
#define D18F3xF4_Reserved_31_0_WIDTH 32
#define D18F3xF4_Reserved_31_0_MASK 0xffffffff
/// D18F3xF4
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3xF4_STRUCT;
// **** D18F3xF8 Register Definition ****
// Address
#define D18F3xF8_ADDRESS 0xf8
// Type
#define D18F3xF8_TYPE TYPE_D18F3
// Field Data
#define D18F3xF8_Reserved_31_0_OFFSET 0
#define D18F3xF8_Reserved_31_0_WIDTH 32
#define D18F3xF8_Reserved_31_0_MASK 0xffffffff
/// D18F3xF8
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3xF8_STRUCT;
// **** D18F3xFC Register Definition ****
// Address
#define D18F3xFC_ADDRESS 0xfc
// Type
#define D18F3xFC_TYPE TYPE_D18F3
// Field Data
#define D18F3xFC_Stepping_OFFSET 0
#define D18F3xFC_Stepping_WIDTH 4
#define D18F3xFC_Stepping_MASK 0xf
#define D18F3xFC_BaseModel_OFFSET 4
#define D18F3xFC_BaseModel_WIDTH 4
#define D18F3xFC_BaseModel_MASK 0xf0
#define D18F3xFC_BaseFamily_OFFSET 8
#define D18F3xFC_BaseFamily_WIDTH 4
#define D18F3xFC_BaseFamily_MASK 0xf00
#define D18F3xFC_Reserved_15_12_OFFSET 12
#define D18F3xFC_Reserved_15_12_WIDTH 4
#define D18F3xFC_Reserved_15_12_MASK 0xf000
#define D18F3xFC_ExtModel_OFFSET 16
#define D18F3xFC_ExtModel_WIDTH 4
#define D18F3xFC_ExtModel_MASK 0xf0000
#define D18F3xFC_ExtFamily_OFFSET 20
#define D18F3xFC_ExtFamily_WIDTH 8
#define D18F3xFC_ExtFamily_MASK 0xff00000
#define D18F3xFC_Reserved_31_28_OFFSET 28
#define D18F3xFC_Reserved_31_28_WIDTH 4
#define D18F3xFC_Reserved_31_28_MASK 0xf0000000
/// D18F3xFC
typedef union {
struct { ///<
UINT32 Stepping:4 ; ///<
UINT32 BaseModel:4 ; ///<
UINT32 BaseFamily:4 ; ///<
UINT32 Reserved_15_12:4 ; ///<
UINT32 ExtModel:4 ; ///<
UINT32 ExtFamily:8 ; ///<
UINT32 Reserved_31_28:4 ; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3xFC_STRUCT;
// **** D18F3x1CC Register Definition ****
// Address
#define D18F3x1CC_ADDRESS 0x1cc
// Type
#define D18F3x1CC_TYPE TYPE_D18F3
// Field Data
#define D18F3x1CC_LvtOffset_OFFSET 0
#define D18F3x1CC_LvtOffset_WIDTH 4
#define D18F3x1CC_LvtOffset_MASK 0xf
#define D18F3x1CC_Reserved_7_4_OFFSET 4
#define D18F3x1CC_Reserved_7_4_WIDTH 4
#define D18F3x1CC_Reserved_7_4_MASK 0xf0
#define D18F3x1CC_LvtOffsetVal_OFFSET 8
#define D18F3x1CC_LvtOffsetVal_WIDTH 1
#define D18F3x1CC_LvtOffsetVal_MASK 0x100
#define D18F3x1CC_Reserved_31_9_OFFSET 9
#define D18F3x1CC_Reserved_31_9_WIDTH 23
#define D18F3x1CC_Reserved_31_9_MASK 0xfffffe00
/// D18F3x1CC
typedef union {
struct { ///<
UINT32 LvtOffset:4 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 LvtOffsetVal:1 ; ///<
UINT32 Reserved_31_9:23; ///<
} Field; ///<
UINT32 Value; ///<
} D18F3x1CC_STRUCT;
// **** DxF0x00 Register Definition ****
// Address
#define DxF0x00_ADDRESS 0x0
// Type
#define DxF0x00_TYPE TYPE_D4F0
// Field Data
#define DxF0x00_VendorID_OFFSET 0
#define DxF0x00_VendorID_WIDTH 16
#define DxF0x00_VendorID_MASK 0xffff
#define DxF0x00_DeviceID_OFFSET 16
#define DxF0x00_DeviceID_WIDTH 16
#define DxF0x00_DeviceID_MASK 0xffff0000
/// DxF0x00
typedef union {
struct { ///<
UINT32 VendorID:16; ///<
UINT32 DeviceID:16; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x00_STRUCT;
// **** DxF0x08 Register Definition ****
// Address
#define DxF0x08_ADDRESS 0x8
// Type
#define DxF0x08_TYPE TYPE_D4F0
// Field Data
#define DxF0x08_RevID_OFFSET 0
#define DxF0x08_RevID_WIDTH 8
#define DxF0x08_RevID_MASK 0xff
#define DxF0x08_ClassCode_OFFSET 8
#define DxF0x08_ClassCode_WIDTH 24
#define DxF0x08_ClassCode_MASK 0xffffff00
/// DxF0x08
typedef union {
struct { ///<
UINT32 RevID:8 ; ///<
UINT32 ClassCode:24; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x08_STRUCT;
// **** DxF0x0C Register Definition ****
// Address
#define DxF0x0C_ADDRESS 0xc
// Type
#define DxF0x0C_TYPE TYPE_D4F0
// Field Data
#define DxF0x0C_CacheLineSize_OFFSET 0
#define DxF0x0C_CacheLineSize_WIDTH 8
#define DxF0x0C_CacheLineSize_MASK 0xff
#define DxF0x0C_LatencyTimer_OFFSET 8
#define DxF0x0C_LatencyTimer_WIDTH 8
#define DxF0x0C_LatencyTimer_MASK 0xff00
#define DxF0x0C_HeaderTypeReg_OFFSET 16
#define DxF0x0C_HeaderTypeReg_WIDTH 8
#define DxF0x0C_HeaderTypeReg_MASK 0xff0000
#define DxF0x0C_BIST_OFFSET 24
#define DxF0x0C_BIST_WIDTH 8
#define DxF0x0C_BIST_MASK 0xff000000
/// DxF0x0C
typedef union {
struct { ///<
UINT32 CacheLineSize:8 ; ///<
UINT32 LatencyTimer:8 ; ///<
UINT32 HeaderTypeReg:8 ; ///<
UINT32 BIST:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x0C_STRUCT;
// **** DxF0x18 Register Definition ****
// Address
#define DxF0x18_ADDRESS 0x18
// Type
#define DxF0x18_TYPE TYPE_D4F0
// Field Data
#define DxF0x18_PrimaryBus_OFFSET 0
#define DxF0x18_PrimaryBus_WIDTH 8
#define DxF0x18_PrimaryBus_MASK 0xff
#define DxF0x18_SecondaryBus_OFFSET 8
#define DxF0x18_SecondaryBus_WIDTH 8
#define DxF0x18_SecondaryBus_MASK 0xff00
#define DxF0x18_SubBusNumber_OFFSET 16
#define DxF0x18_SubBusNumber_WIDTH 8
#define DxF0x18_SubBusNumber_MASK 0xff0000
#define DxF0x18_SecondaryLatencyTimer_OFFSET 24
#define DxF0x18_SecondaryLatencyTimer_WIDTH 8
#define DxF0x18_SecondaryLatencyTimer_MASK 0xff000000
/// DxF0x18
typedef union {
struct { ///<
UINT32 PrimaryBus:8 ; ///<
UINT32 SecondaryBus:8 ; ///<
UINT32 SubBusNumber:8 ; ///<
UINT32 SecondaryLatencyTimer:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x18_STRUCT;
// **** DxF0x20 Register Definition ****
// Address
#define DxF0x20_ADDRESS 0x20
// Type
#define DxF0x20_TYPE TYPE_D4F0
// Field Data
#define DxF0x20_Reserved_3_0_OFFSET 0
#define DxF0x20_Reserved_3_0_WIDTH 4
#define DxF0x20_Reserved_3_0_MASK 0xf
#define DxF0x20_MemBase_OFFSET 4
#define DxF0x20_MemBase_WIDTH 12
#define DxF0x20_MemBase_MASK 0xfff0
#define DxF0x20_Reserved_19_16_OFFSET 16
#define DxF0x20_Reserved_19_16_WIDTH 4
#define DxF0x20_Reserved_19_16_MASK 0xf0000
#define DxF0x20_MemLimit_OFFSET 20
#define DxF0x20_MemLimit_WIDTH 12
#define DxF0x20_MemLimit_MASK 0xfff00000
/// DxF0x20
typedef union {
struct { ///<
UINT32 Reserved_3_0:4 ; ///<
UINT32 MemBase:12; ///<
UINT32 Reserved_19_16:4 ; ///<
UINT32 MemLimit:12; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x20_STRUCT;
// **** DxF0x24 Register Definition ****
// Address
#define DxF0x24_ADDRESS 0x24
// Type
#define DxF0x24_TYPE TYPE_D4F0
// Field Data
#define DxF0x24_PrefMemBaseR_OFFSET 0
#define DxF0x24_PrefMemBaseR_WIDTH 4
#define DxF0x24_PrefMemBaseR_MASK 0xf
#define DxF0x24_PrefMemBase_31_20__OFFSET 4
#define DxF0x24_PrefMemBase_31_20__WIDTH 12
#define DxF0x24_PrefMemBase_31_20__MASK 0xfff0
#define DxF0x24_PrefMemLimitR_OFFSET 16
#define DxF0x24_PrefMemLimitR_WIDTH 4
#define DxF0x24_PrefMemLimitR_MASK 0xf0000
#define DxF0x24_PrefMemLimit_OFFSET 20
#define DxF0x24_PrefMemLimit_WIDTH 12
#define DxF0x24_PrefMemLimit_MASK 0xfff00000
/// DxF0x24
typedef union {
struct { ///<
UINT32 PrefMemBaseR:4 ; ///<
UINT32 PrefMemBase_31_20_:12; ///<
UINT32 PrefMemLimitR:4 ; ///<
UINT32 PrefMemLimit:12; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x24_STRUCT;
// **** DxF0x28 Register Definition ****
// Address
#define DxF0x28_ADDRESS 0x28
// Type
#define DxF0x28_TYPE TYPE_D4F0
// Field Data
#define DxF0x28_PrefMemBase_63_32__OFFSET 0
#define DxF0x28_PrefMemBase_63_32__WIDTH 32
#define DxF0x28_PrefMemBase_63_32__MASK 0xffffffff
/// DxF0x28
typedef union {
struct { ///<
UINT32 PrefMemBase_63_32_:32; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x28_STRUCT;
// **** DxF0x2C Register Definition ****
// Address
#define DxF0x2C_ADDRESS 0x2c
// Type
#define DxF0x2C_TYPE TYPE_D4F0
// Field Data
#define DxF0x2C_PrefMemLimit_63_32__OFFSET 0
#define DxF0x2C_PrefMemLimit_63_32__WIDTH 32
#define DxF0x2C_PrefMemLimit_63_32__MASK 0xffffffff
/// DxF0x2C
typedef union {
struct { ///<
UINT32 PrefMemLimit_63_32_:32; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x2C_STRUCT;
// **** DxF0x30 Register Definition ****
// Address
#define DxF0x30_ADDRESS 0x30
// Type
#define DxF0x30_TYPE TYPE_D4F0
// Field Data
#define DxF0x30_IOBase_31_16__OFFSET 0
#define DxF0x30_IOBase_31_16__WIDTH 16
#define DxF0x30_IOBase_31_16__MASK 0xffff
#define DxF0x30_IOLimit_31_16__OFFSET 16
#define DxF0x30_IOLimit_31_16__WIDTH 16
#define DxF0x30_IOLimit_31_16__MASK 0xffff0000
/// DxF0x30
typedef union {
struct { ///<
UINT32 IOBase_31_16_:16; ///<
UINT32 IOLimit_31_16_:16; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x30_STRUCT;
// **** DxF0x34 Register Definition ****
// Address
#define DxF0x34_ADDRESS 0x34
// Type
#define DxF0x34_TYPE TYPE_D4F0
// Field Data
#define DxF0x34_CapPtr_OFFSET 0
#define DxF0x34_CapPtr_WIDTH 8
#define DxF0x34_CapPtr_MASK 0xff
#define DxF0x34_Reserved_31_8_OFFSET 8
#define DxF0x34_Reserved_31_8_WIDTH 24
#define DxF0x34_Reserved_31_8_MASK 0xffffff00
/// DxF0x34
typedef union {
struct { ///<
UINT32 CapPtr:8 ; ///<
UINT32 Reserved_31_8:24; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x34_STRUCT;
// **** DxF0x3C Register Definition ****
// Address
#define DxF0x3C_ADDRESS 0x3c
// Type
#define DxF0x3C_TYPE TYPE_D4F0
// Field Data
#define DxF0x3C_IntLine_OFFSET 0
#define DxF0x3C_IntLine_WIDTH 8
#define DxF0x3C_IntLine_MASK 0xff
#define DxF0x3C_IntPin_OFFSET 8
#define DxF0x3C_IntPin_WIDTH 3
#define DxF0x3C_IntPin_MASK 0x700
#define DxF0x3C_IntPinR_OFFSET 11
#define DxF0x3C_IntPinR_WIDTH 5
#define DxF0x3C_IntPinR_MASK 0xf800
#define DxF0x3C_ParityResponseEn_OFFSET 16
#define DxF0x3C_ParityResponseEn_WIDTH 1
#define DxF0x3C_ParityResponseEn_MASK 0x10000
#define DxF0x3C_SerrEn_OFFSET 17
#define DxF0x3C_SerrEn_WIDTH 1
#define DxF0x3C_SerrEn_MASK 0x20000
#define DxF0x3C_IsaEn_OFFSET 18
#define DxF0x3C_IsaEn_WIDTH 1
#define DxF0x3C_IsaEn_MASK 0x40000
#define DxF0x3C_VgaEn_OFFSET 19
#define DxF0x3C_VgaEn_WIDTH 1
#define DxF0x3C_VgaEn_MASK 0x80000
#define DxF0x3C_Vga16En_OFFSET 20
#define DxF0x3C_Vga16En_WIDTH 1
#define DxF0x3C_Vga16En_MASK 0x100000
#define DxF0x3C_MasterAbortMode_OFFSET 21
#define DxF0x3C_MasterAbortMode_WIDTH 1
#define DxF0x3C_MasterAbortMode_MASK 0x200000
#define DxF0x3C_SecondaryBusReset_OFFSET 22
#define DxF0x3C_SecondaryBusReset_WIDTH 1
#define DxF0x3C_SecondaryBusReset_MASK 0x400000
#define DxF0x3C_FastB2BCap_OFFSET 23
#define DxF0x3C_FastB2BCap_WIDTH 1
#define DxF0x3C_FastB2BCap_MASK 0x800000
#define DxF0x3C_Reserved_31_24_OFFSET 24
#define DxF0x3C_Reserved_31_24_WIDTH 8
#define DxF0x3C_Reserved_31_24_MASK 0xff000000
/// DxF0x3C
typedef union {
struct { ///<
UINT32 IntLine:8 ; ///<
UINT32 IntPin:3 ; ///<
UINT32 IntPinR:5 ; ///<
UINT32 ParityResponseEn:1 ; ///<
UINT32 SerrEn:1 ; ///<
UINT32 IsaEn:1 ; ///<
UINT32 VgaEn:1 ; ///<
UINT32 Vga16En:1 ; ///<
UINT32 MasterAbortMode:1 ; ///<
UINT32 SecondaryBusReset:1 ; ///<
UINT32 FastB2BCap:1 ; ///<
UINT32 Reserved_31_24:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x3C_STRUCT;
// **** DxF0x50 Register Definition ****
// Address
#define DxF0x50_ADDRESS 0x50
// Type
#define DxF0x50_TYPE TYPE_D4F0
// Field Data
#define DxF0x50_CapID_OFFSET 0
#define DxF0x50_CapID_WIDTH 8
#define DxF0x50_CapID_MASK 0xff
#define DxF0x50_NextPtr_OFFSET 8
#define DxF0x50_NextPtr_WIDTH 8
#define DxF0x50_NextPtr_MASK 0xff00
#define DxF0x50_Version_OFFSET 16
#define DxF0x50_Version_WIDTH 3
#define DxF0x50_Version_MASK 0x70000
#define DxF0x50_PmeClock_OFFSET 19
#define DxF0x50_PmeClock_WIDTH 1
#define DxF0x50_PmeClock_MASK 0x80000
#define DxF0x50_Reserved_20_20_OFFSET 20
#define DxF0x50_Reserved_20_20_WIDTH 1
#define DxF0x50_Reserved_20_20_MASK 0x100000
#define DxF0x50_DevSpecificInit_OFFSET 21
#define DxF0x50_DevSpecificInit_WIDTH 1
#define DxF0x50_DevSpecificInit_MASK 0x200000
#define DxF0x50_AuxCurrent_OFFSET 22
#define DxF0x50_AuxCurrent_WIDTH 3
#define DxF0x50_AuxCurrent_MASK 0x1c00000
#define DxF0x50_D1Support_OFFSET 25
#define DxF0x50_D1Support_WIDTH 1
#define DxF0x50_D1Support_MASK 0x2000000
#define DxF0x50_D2Support_OFFSET 26
#define DxF0x50_D2Support_WIDTH 1
#define DxF0x50_D2Support_MASK 0x4000000
#define DxF0x50_PmeSupport_OFFSET 27
#define DxF0x50_PmeSupport_WIDTH 5
#define DxF0x50_PmeSupport_MASK 0xf8000000
/// DxF0x50
typedef union {
struct { ///<
UINT32 CapID:8 ; ///<
UINT32 NextPtr:8 ; ///<
UINT32 Version:3 ; ///<
UINT32 PmeClock:1 ; ///<
UINT32 Reserved_20_20:1 ; ///<
UINT32 DevSpecificInit:1 ; ///<
UINT32 AuxCurrent:3 ; ///<
UINT32 D1Support:1 ; ///<
UINT32 D2Support:1 ; ///<
UINT32 PmeSupport:5 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x50_STRUCT;
// **** DxF0x54 Register Definition ****
// Address
#define DxF0x54_ADDRESS 0x54
// Type
#define DxF0x54_TYPE TYPE_D4F0
// Field Data
#define DxF0x54_PowerState_OFFSET 0
#define DxF0x54_PowerState_WIDTH 2
#define DxF0x54_PowerState_MASK 0x3
#define DxF0x54_Reserved_2_2_OFFSET 2
#define DxF0x54_Reserved_2_2_WIDTH 1
#define DxF0x54_Reserved_2_2_MASK 0x4
#define DxF0x54_NoSoftReset_OFFSET 3
#define DxF0x54_NoSoftReset_WIDTH 1
#define DxF0x54_NoSoftReset_MASK 0x8
#define DxF0x54_Reserved_7_4_OFFSET 4
#define DxF0x54_Reserved_7_4_WIDTH 4
#define DxF0x54_Reserved_7_4_MASK 0xf0
#define DxF0x54_PmeEn_OFFSET 8
#define DxF0x54_PmeEn_WIDTH 1
#define DxF0x54_PmeEn_MASK 0x100
#define DxF0x54_DataSelect_OFFSET 9
#define DxF0x54_DataSelect_WIDTH 4
#define DxF0x54_DataSelect_MASK 0x1e00
#define DxF0x54_DataScale_OFFSET 13
#define DxF0x54_DataScale_WIDTH 2
#define DxF0x54_DataScale_MASK 0x6000
#define DxF0x54_PmeStatus_OFFSET 15
#define DxF0x54_PmeStatus_WIDTH 1
#define DxF0x54_PmeStatus_MASK 0x8000
#define DxF0x54_Reserved_21_16_OFFSET 16
#define DxF0x54_Reserved_21_16_WIDTH 6
#define DxF0x54_Reserved_21_16_MASK 0x3f0000
#define DxF0x54_B2B3Support_OFFSET 22
#define DxF0x54_B2B3Support_WIDTH 1
#define DxF0x54_B2B3Support_MASK 0x400000
#define DxF0x54_BusPwrEn_OFFSET 23
#define DxF0x54_BusPwrEn_WIDTH 1
#define DxF0x54_BusPwrEn_MASK 0x800000
#define DxF0x54_PmeData_OFFSET 24
#define DxF0x54_PmeData_WIDTH 8
#define DxF0x54_PmeData_MASK 0xff000000
/// DxF0x54
typedef union {
struct { ///<
UINT32 PowerState:2 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 NoSoftReset:1 ; ///<
UINT32 Reserved_7_4:4 ; ///<
UINT32 PmeEn:1 ; ///<
UINT32 DataSelect:4 ; ///<
UINT32 DataScale:2 ; ///<
UINT32 PmeStatus:1 ; ///<
UINT32 Reserved_21_16:6 ; ///<
UINT32 B2B3Support:1 ; ///<
UINT32 BusPwrEn:1 ; ///<
UINT32 PmeData:8 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x54_STRUCT;
// **** DxF0x58 Register Definition ****
// Address
#define DxF0x58_ADDRESS 0x58
// Type
#define DxF0x58_TYPE TYPE_D4F0
// Field Data
#define DxF0x58_CapID_OFFSET 0
#define DxF0x58_CapID_WIDTH 8
#define DxF0x58_CapID_MASK 0xff
#define DxF0x58_NextPtr_OFFSET 8
#define DxF0x58_NextPtr_WIDTH 8
#define DxF0x58_NextPtr_MASK 0xff00
#define DxF0x58_Version_OFFSET 16
#define DxF0x58_Version_WIDTH 4
#define DxF0x58_Version_MASK 0xf0000
#define DxF0x58_DeviceType_OFFSET 20
#define DxF0x58_DeviceType_WIDTH 4
#define DxF0x58_DeviceType_MASK 0xf00000
#define DxF0x58_SlotImplemented_OFFSET 24
#define DxF0x58_SlotImplemented_WIDTH 1
#define DxF0x58_SlotImplemented_MASK 0x1000000
#define DxF0x58_IntMessageNum_OFFSET 25
#define DxF0x58_IntMessageNum_WIDTH 5
#define DxF0x58_IntMessageNum_MASK 0x3e000000
#define DxF0x58_Reserved_31_30_OFFSET 30
#define DxF0x58_Reserved_31_30_WIDTH 2
#define DxF0x58_Reserved_31_30_MASK 0xc0000000
/// DxF0x58
typedef union {
struct { ///<
UINT32 CapID:8 ; ///<
UINT32 NextPtr:8 ; ///<
UINT32 Version:4 ; ///<
UINT32 DeviceType:4 ; ///<
UINT32 SlotImplemented:1 ; ///<
UINT32 IntMessageNum:5 ; ///<
UINT32 Reserved_31_30:2 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x58_STRUCT;
// **** DxF0x5C Register Definition ****
// Address
#define DxF0x5C_ADDRESS 0x5c
// Type
#define DxF0x5C_TYPE TYPE_D4F0
// Field Data
#define DxF0x5C_MaxPayloadSupport_OFFSET 0
#define DxF0x5C_MaxPayloadSupport_WIDTH 3
#define DxF0x5C_MaxPayloadSupport_MASK 0x7
#define DxF0x5C_PhantomFunc_OFFSET 3
#define DxF0x5C_PhantomFunc_WIDTH 2
#define DxF0x5C_PhantomFunc_MASK 0x18
#define DxF0x5C_ExtendedTag_OFFSET 5
#define DxF0x5C_ExtendedTag_WIDTH 1
#define DxF0x5C_ExtendedTag_MASK 0x20
#define DxF0x5C_L0SAcceptableLatency_OFFSET 6
#define DxF0x5C_L0SAcceptableLatency_WIDTH 3
#define DxF0x5C_L0SAcceptableLatency_MASK 0x1c0
#define DxF0x5C_L1AcceptableLatency_OFFSET 9
#define DxF0x5C_L1AcceptableLatency_WIDTH 3
#define DxF0x5C_L1AcceptableLatency_MASK 0xe00
#define DxF0x5C_Reserved_14_12_OFFSET 12
#define DxF0x5C_Reserved_14_12_WIDTH 3
#define DxF0x5C_Reserved_14_12_MASK 0x7000
#define DxF0x5C_RoleBasedErrReporting_OFFSET 15
#define DxF0x5C_RoleBasedErrReporting_WIDTH 1
#define DxF0x5C_RoleBasedErrReporting_MASK 0x8000
#define DxF0x5C_Reserved_17_16_OFFSET 16
#define DxF0x5C_Reserved_17_16_WIDTH 2
#define DxF0x5C_Reserved_17_16_MASK 0x30000
#define DxF0x5C_CapturedSlotPowerLimit_OFFSET 18
#define DxF0x5C_CapturedSlotPowerLimit_WIDTH 8
#define DxF0x5C_CapturedSlotPowerLimit_MASK 0x3fc0000
#define DxF0x5C_CapturedSlotPowerScale_OFFSET 26
#define DxF0x5C_CapturedSlotPowerScale_WIDTH 2
#define DxF0x5C_CapturedSlotPowerScale_MASK 0xc000000
#define DxF0x5C_FlrCapable_OFFSET 28
#define DxF0x5C_FlrCapable_WIDTH 1
#define DxF0x5C_FlrCapable_MASK 0x10000000
#define DxF0x5C_Reserved_31_29_OFFSET 29
#define DxF0x5C_Reserved_31_29_WIDTH 3
#define DxF0x5C_Reserved_31_29_MASK 0xe0000000
/// DxF0x5C
typedef union {
struct { ///<
UINT32 MaxPayloadSupport:3 ; ///<
UINT32 PhantomFunc:2 ; ///<
UINT32 ExtendedTag:1 ; ///<
UINT32 L0SAcceptableLatency:3 ; ///<
UINT32 L1AcceptableLatency:3 ; ///<
UINT32 Reserved_14_12:3 ; ///<
UINT32 RoleBasedErrReporting:1 ; ///<
UINT32 Reserved_17_16:2 ; ///<
UINT32 CapturedSlotPowerLimit:8 ; ///<
UINT32 CapturedSlotPowerScale:2 ; ///<
UINT32 FlrCapable:1 ; ///<
UINT32 Reserved_31_29:3 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x5C_STRUCT;
// **** DxF0x60 Register Definition ****
// Address
#define DxF0x60_ADDRESS 0x60
// Type
#define DxF0x60_TYPE TYPE_D4F0
// Field Data
#define DxF0x60_CorrErrEn_OFFSET 0
#define DxF0x60_CorrErrEn_WIDTH 1
#define DxF0x60_CorrErrEn_MASK 0x1
#define DxF0x60_NonFatalErrEn_OFFSET 1
#define DxF0x60_NonFatalErrEn_WIDTH 1
#define DxF0x60_NonFatalErrEn_MASK 0x2
#define DxF0x60_FatalErrEn_OFFSET 2
#define DxF0x60_FatalErrEn_WIDTH 1
#define DxF0x60_FatalErrEn_MASK 0x4
#define DxF0x60_UsrReportEn_OFFSET 3
#define DxF0x60_UsrReportEn_WIDTH 1
#define DxF0x60_UsrReportEn_MASK 0x8
#define DxF0x60_RelaxedOrdEn_OFFSET 4
#define DxF0x60_RelaxedOrdEn_WIDTH 1
#define DxF0x60_RelaxedOrdEn_MASK 0x10
#define DxF0x60_MaxPayloadSize_OFFSET 5
#define DxF0x60_MaxPayloadSize_WIDTH 3
#define DxF0x60_MaxPayloadSize_MASK 0xe0
#define DxF0x60_ExtendedTagEn_OFFSET 8
#define DxF0x60_ExtendedTagEn_WIDTH 1
#define DxF0x60_ExtendedTagEn_MASK 0x100
#define DxF0x60_PhantomFuncEn_OFFSET 9
#define DxF0x60_PhantomFuncEn_WIDTH 1
#define DxF0x60_PhantomFuncEn_MASK 0x200
#define DxF0x60_AuxPowerPmEn_OFFSET 10
#define DxF0x60_AuxPowerPmEn_WIDTH 1
#define DxF0x60_AuxPowerPmEn_MASK 0x400
#define DxF0x60_NoSnoopEnable_OFFSET 11
#define DxF0x60_NoSnoopEnable_WIDTH 1
#define DxF0x60_NoSnoopEnable_MASK 0x800
#define DxF0x60_MaxRequestSize_OFFSET 12
#define DxF0x60_MaxRequestSize_WIDTH 3
#define DxF0x60_MaxRequestSize_MASK 0x7000
#define DxF0x60_BridgeCfgRetryEn_OFFSET 15
#define DxF0x60_BridgeCfgRetryEn_WIDTH 1
#define DxF0x60_BridgeCfgRetryEn_MASK 0x8000
#define DxF0x60_CorrErr_OFFSET 16
#define DxF0x60_CorrErr_WIDTH 1
#define DxF0x60_CorrErr_MASK 0x10000
#define DxF0x60_NonFatalErr_OFFSET 17
#define DxF0x60_NonFatalErr_WIDTH 1
#define DxF0x60_NonFatalErr_MASK 0x20000
#define DxF0x60_FatalErr_OFFSET 18
#define DxF0x60_FatalErr_WIDTH 1
#define DxF0x60_FatalErr_MASK 0x40000
#define DxF0x60_UsrDetected_OFFSET 19
#define DxF0x60_UsrDetected_WIDTH 1
#define DxF0x60_UsrDetected_MASK 0x80000
#define DxF0x60_AuxPwr_OFFSET 20
#define DxF0x60_AuxPwr_WIDTH 1
#define DxF0x60_AuxPwr_MASK 0x100000
#define DxF0x60_TransactionsPending_OFFSET 21
#define DxF0x60_TransactionsPending_WIDTH 1
#define DxF0x60_TransactionsPending_MASK 0x200000
#define DxF0x60_Reserved_31_22_OFFSET 22
#define DxF0x60_Reserved_31_22_WIDTH 10
#define DxF0x60_Reserved_31_22_MASK 0xffc00000
/// DxF0x60
typedef union {
struct { ///<
UINT32 CorrErrEn:1 ; ///<
UINT32 NonFatalErrEn:1 ; ///<
UINT32 FatalErrEn:1 ; ///<
UINT32 UsrReportEn:1 ; ///<
UINT32 RelaxedOrdEn:1 ; ///<
UINT32 MaxPayloadSize:3 ; ///<
UINT32 ExtendedTagEn:1 ; ///<
UINT32 PhantomFuncEn:1 ; ///<
UINT32 AuxPowerPmEn:1 ; ///<
UINT32 NoSnoopEnable:1 ; ///<
UINT32 MaxRequestSize:3 ; ///<
UINT32 BridgeCfgRetryEn:1 ; ///<
UINT32 CorrErr:1 ; ///<
UINT32 NonFatalErr:1 ; ///<
UINT32 FatalErr:1 ; ///<
UINT32 UsrDetected:1 ; ///<
UINT32 AuxPwr:1 ; ///<
UINT32 TransactionsPending:1 ; ///<
UINT32 Reserved_31_22:10; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x60_STRUCT;
// **** DxF0x68 Register Definition ****
// Address
#define DxF0x68_ADDRESS 0x68
// Type
#define DxF0x68_TYPE TYPE_D4F0
// Field Data
#define DxF0x68_PmControl_OFFSET 0
#define DxF0x68_PmControl_WIDTH 2
#define DxF0x68_PmControl_MASK 0x3
#define DxF0x68_Reserved_2_2_OFFSET 2
#define DxF0x68_Reserved_2_2_WIDTH 1
#define DxF0x68_Reserved_2_2_MASK 0x4
#define DxF0x68_ReadCplBoundary_OFFSET 3
#define DxF0x68_ReadCplBoundary_WIDTH 1
#define DxF0x68_ReadCplBoundary_MASK 0x8
#define DxF0x68_LinkDis_OFFSET 4
#define DxF0x68_LinkDis_WIDTH 1
#define DxF0x68_LinkDis_MASK 0x10
#define DxF0x68_RetrainLink_OFFSET 5
#define DxF0x68_RetrainLink_WIDTH 1
#define DxF0x68_RetrainLink_MASK 0x20
#define DxF0x68_CommonClockCfg_OFFSET 6
#define DxF0x68_CommonClockCfg_WIDTH 1
#define DxF0x68_CommonClockCfg_MASK 0x40
#define DxF0x68_ExtendedSync_OFFSET 7
#define DxF0x68_ExtendedSync_WIDTH 1
#define DxF0x68_ExtendedSync_MASK 0x80
#define DxF0x68_ClockPowerManagementEn_OFFSET 8
#define DxF0x68_ClockPowerManagementEn_WIDTH 1
#define DxF0x68_ClockPowerManagementEn_MASK 0x100
#define DxF0x68_HWAutonomousWidthDisable_OFFSET 9
#define DxF0x68_HWAutonomousWidthDisable_WIDTH 1
#define DxF0x68_HWAutonomousWidthDisable_MASK 0x200
#define DxF0x68_LinkBWManagementEn_OFFSET 10
#define DxF0x68_LinkBWManagementEn_WIDTH 1
#define DxF0x68_LinkBWManagementEn_MASK 0x400
#define DxF0x68_LinkAutonomousBWIntEn_OFFSET 11
#define DxF0x68_LinkAutonomousBWIntEn_WIDTH 1
#define DxF0x68_LinkAutonomousBWIntEn_MASK 0x800
#define DxF0x68_Reserved_15_12_OFFSET 12
#define DxF0x68_Reserved_15_12_WIDTH 4
#define DxF0x68_Reserved_15_12_MASK 0xf000
#define DxF0x68_LinkSpeed_OFFSET 16
#define DxF0x68_LinkSpeed_WIDTH 4
#define DxF0x68_LinkSpeed_MASK 0xf0000
#define DxF0x68_NegotiatedLinkWidth_OFFSET 20
#define DxF0x68_NegotiatedLinkWidth_WIDTH 6
#define DxF0x68_NegotiatedLinkWidth_MASK 0x3f00000
#define DxF0x68_Reserved_26_26_OFFSET 26
#define DxF0x68_Reserved_26_26_WIDTH 1
#define DxF0x68_Reserved_26_26_MASK 0x4000000
#define DxF0x68_LinkTraining_OFFSET 27
#define DxF0x68_LinkTraining_WIDTH 1
#define DxF0x68_LinkTraining_MASK 0x8000000
#define DxF0x68_SlotClockCfg_OFFSET 28
#define DxF0x68_SlotClockCfg_WIDTH 1
#define DxF0x68_SlotClockCfg_MASK 0x10000000
#define DxF0x68_DlActive_OFFSET 29
#define DxF0x68_DlActive_WIDTH 1
#define DxF0x68_DlActive_MASK 0x20000000
#define DxF0x68_LinkBWManagementStatus_OFFSET 30
#define DxF0x68_LinkBWManagementStatus_WIDTH 1
#define DxF0x68_LinkBWManagementStatus_MASK 0x40000000
#define DxF0x68_LinkAutonomousBWStatus_OFFSET 31
#define DxF0x68_LinkAutonomousBWStatus_WIDTH 1
#define DxF0x68_LinkAutonomousBWStatus_MASK 0x80000000
/// DxF0x68
typedef union {
struct { ///<
UINT32 PmControl:2 ; ///<
UINT32 Reserved_2_2:1 ; ///<
UINT32 ReadCplBoundary:1 ; ///<
UINT32 LinkDis:1 ; ///<
UINT32 RetrainLink:1 ; ///<
UINT32 CommonClockCfg:1 ; ///<
UINT32 ExtendedSync:1 ; ///<
UINT32 ClockPowerManagementEn:1 ; ///<
UINT32 HWAutonomousWidthDisable:1 ; ///<
UINT32 LinkBWManagementEn:1 ; ///<
UINT32 LinkAutonomousBWIntEn:1 ; ///<
UINT32 Reserved_15_12:4 ; ///<
UINT32 LinkSpeed:4 ; ///<
UINT32 NegotiatedLinkWidth:6 ; ///<
UINT32 Reserved_26_26:1 ; ///<
UINT32 LinkTraining:1 ; ///<
UINT32 SlotClockCfg:1 ; ///<
UINT32 DlActive:1 ; ///<
UINT32 LinkBWManagementStatus:1 ; ///<
UINT32 LinkAutonomousBWStatus:1 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x68_STRUCT;
// **** DxF0x6C Register Definition ****
// Address
#define DxF0x6C_ADDRESS 0x6c
// Type
#define DxF0x6C_TYPE TYPE_D4F0
// Field Data
#define DxF0x6C_AttnButtonPresent_OFFSET 0
#define DxF0x6C_AttnButtonPresent_WIDTH 1
#define DxF0x6C_AttnButtonPresent_MASK 0x1
#define DxF0x6C_PwrControllerPresent_OFFSET 1
#define DxF0x6C_PwrControllerPresent_WIDTH 1
#define DxF0x6C_PwrControllerPresent_MASK 0x2
#define DxF0x6C_MrlSensorPresent_OFFSET 2
#define DxF0x6C_MrlSensorPresent_WIDTH 1
#define DxF0x6C_MrlSensorPresent_MASK 0x4
#define DxF0x6C_AttnIndicatorPresent_OFFSET 3
#define DxF0x6C_AttnIndicatorPresent_WIDTH 1
#define DxF0x6C_AttnIndicatorPresent_MASK 0x8
#define DxF0x6C_PwrIndicatorPresent_OFFSET 4
#define DxF0x6C_PwrIndicatorPresent_WIDTH 1
#define DxF0x6C_PwrIndicatorPresent_MASK 0x10
#define DxF0x6C_HotplugSurprise_OFFSET 5
#define DxF0x6C_HotplugSurprise_WIDTH 1
#define DxF0x6C_HotplugSurprise_MASK 0x20
#define DxF0x6C_HotplugCapable_OFFSET 6
#define DxF0x6C_HotplugCapable_WIDTH 1
#define DxF0x6C_HotplugCapable_MASK 0x40
#define DxF0x6C_SlotPwrLimitValue_OFFSET 7
#define DxF0x6C_SlotPwrLimitValue_WIDTH 8
#define DxF0x6C_SlotPwrLimitValue_MASK 0x7f80
#define DxF0x6C_SlotPwrLimitScale_OFFSET 15
#define DxF0x6C_SlotPwrLimitScale_WIDTH 2
#define DxF0x6C_SlotPwrLimitScale_MASK 0x18000
#define DxF0x6C_ElecMechIlPresent_OFFSET 17
#define DxF0x6C_ElecMechIlPresent_WIDTH 1
#define DxF0x6C_ElecMechIlPresent_MASK 0x20000
#define DxF0x6C_NoCmdCplSupport_OFFSET 18
#define DxF0x6C_NoCmdCplSupport_WIDTH 1
#define DxF0x6C_NoCmdCplSupport_MASK 0x40000
#define DxF0x6C_PhysicalSlotNumber_OFFSET 19
#define DxF0x6C_PhysicalSlotNumber_WIDTH 13
#define DxF0x6C_PhysicalSlotNumber_MASK 0xfff80000
/// DxF0x6C
typedef union {
struct { ///<
UINT32 AttnButtonPresent:1 ; ///<
UINT32 PwrControllerPresent:1 ; ///<
UINT32 MrlSensorPresent:1 ; ///<
UINT32 AttnIndicatorPresent:1 ; ///<
UINT32 PwrIndicatorPresent:1 ; ///<
UINT32 HotplugSurprise:1 ; ///<
UINT32 HotplugCapable:1 ; ///<
UINT32 SlotPwrLimitValue:8 ; ///<
UINT32 SlotPwrLimitScale:2 ; ///<
UINT32 ElecMechIlPresent:1 ; ///<
UINT32 NoCmdCplSupport:1 ; ///<
UINT32 PhysicalSlotNumber:13; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x6C_STRUCT;
// **** DxF0x70 Register Definition ****
// Address
#define DxF0x70_ADDRESS 0x70
// Type
#define DxF0x70_TYPE TYPE_D4F0
// Field Data
#define DxF0x70_AttnButtonPressedEn_OFFSET 0
#define DxF0x70_AttnButtonPressedEn_WIDTH 1
#define DxF0x70_AttnButtonPressedEn_MASK 0x1
#define DxF0x70_PwrFaultDetectedEn_OFFSET 1
#define DxF0x70_PwrFaultDetectedEn_WIDTH 1
#define DxF0x70_PwrFaultDetectedEn_MASK 0x2
#define DxF0x70_MrlSensorChangedEn_OFFSET 2
#define DxF0x70_MrlSensorChangedEn_WIDTH 1
#define DxF0x70_MrlSensorChangedEn_MASK 0x4
#define DxF0x70_PresenceDetectChangedEn_OFFSET 3
#define DxF0x70_PresenceDetectChangedEn_WIDTH 1
#define DxF0x70_PresenceDetectChangedEn_MASK 0x8
#define DxF0x70_CmdCplIntrEn_OFFSET 4
#define DxF0x70_CmdCplIntrEn_WIDTH 1
#define DxF0x70_CmdCplIntrEn_MASK 0x10
#define DxF0x70_HotplugIntrEn_OFFSET 5
#define DxF0x70_HotplugIntrEn_WIDTH 1
#define DxF0x70_HotplugIntrEn_MASK 0x20
#define DxF0x70_AttnIndicatorControl_OFFSET 6
#define DxF0x70_AttnIndicatorControl_WIDTH 2
#define DxF0x70_AttnIndicatorControl_MASK 0xc0
#define DxF0x70_PwrIndicatorCntl_OFFSET 8
#define DxF0x70_PwrIndicatorCntl_WIDTH 2
#define DxF0x70_PwrIndicatorCntl_MASK 0x300
#define DxF0x70_PwrControllerCntl_OFFSET 10
#define DxF0x70_PwrControllerCntl_WIDTH 1
#define DxF0x70_PwrControllerCntl_MASK 0x400
#define DxF0x70_ElecMechIlCntl_OFFSET 11
#define DxF0x70_ElecMechIlCntl_WIDTH 1
#define DxF0x70_ElecMechIlCntl_MASK 0x800
#define DxF0x70_DlStateChangedEn_OFFSET 12
#define DxF0x70_DlStateChangedEn_WIDTH 1
#define DxF0x70_DlStateChangedEn_MASK 0x1000
#define DxF0x70_Reserved_15_13_OFFSET 13
#define DxF0x70_Reserved_15_13_WIDTH 3
#define DxF0x70_Reserved_15_13_MASK 0xe000
#define DxF0x70_AttnButtonPressed_OFFSET 16
#define DxF0x70_AttnButtonPressed_WIDTH 1
#define DxF0x70_AttnButtonPressed_MASK 0x10000
#define DxF0x70_PwrFaultDetected_OFFSET 17
#define DxF0x70_PwrFaultDetected_WIDTH 1
#define DxF0x70_PwrFaultDetected_MASK 0x20000
#define DxF0x70_MrlSensorChanged_OFFSET 18
#define DxF0x70_MrlSensorChanged_WIDTH 1
#define DxF0x70_MrlSensorChanged_MASK 0x40000
#define DxF0x70_PresenceDetectChanged_OFFSET 19
#define DxF0x70_PresenceDetectChanged_WIDTH 1
#define DxF0x70_PresenceDetectChanged_MASK 0x80000
#define DxF0x70_CmdCpl_OFFSET 20
#define DxF0x70_CmdCpl_WIDTH 1
#define DxF0x70_CmdCpl_MASK 0x100000
#define DxF0x70_MrlSensorState_OFFSET 21
#define DxF0x70_MrlSensorState_WIDTH 1
#define DxF0x70_MrlSensorState_MASK 0x200000
#define DxF0x70_PresenceDetectState_OFFSET 22
#define DxF0x70_PresenceDetectState_WIDTH 1
#define DxF0x70_PresenceDetectState_MASK 0x400000
#define DxF0x70_ElecMechIlSts_OFFSET 23
#define DxF0x70_ElecMechIlSts_WIDTH 1
#define DxF0x70_ElecMechIlSts_MASK 0x800000
#define DxF0x70_DlStateChanged_OFFSET 24
#define DxF0x70_DlStateChanged_WIDTH 1
#define DxF0x70_DlStateChanged_MASK 0x1000000
#define DxF0x70_Reserved_31_25_OFFSET 25
#define DxF0x70_Reserved_31_25_WIDTH 7
#define DxF0x70_Reserved_31_25_MASK 0xfe000000
/// DxF0x70
typedef union {
struct { ///<
UINT32 AttnButtonPressedEn:1 ; ///<
UINT32 PwrFaultDetectedEn:1 ; ///<
UINT32 MrlSensorChangedEn:1 ; ///<
UINT32 PresenceDetectChangedEn:1 ; ///<
UINT32 CmdCplIntrEn:1 ; ///<
UINT32 HotplugIntrEn:1 ; ///<
UINT32 AttnIndicatorControl:2 ; ///<
UINT32 PwrIndicatorCntl:2 ; ///<
UINT32 PwrControllerCntl:1 ; ///<
UINT32 ElecMechIlCntl:1 ; ///<
UINT32 DlStateChangedEn:1 ; ///<
UINT32 Reserved_15_13:3 ; ///<
UINT32 AttnButtonPressed:1 ; ///<
UINT32 PwrFaultDetected:1 ; ///<
UINT32 MrlSensorChanged:1 ; ///<
UINT32 PresenceDetectChanged:1 ; ///<
UINT32 CmdCpl:1 ; ///<
UINT32 MrlSensorState:1 ; ///<
UINT32 PresenceDetectState:1 ; ///<
UINT32 ElecMechIlSts:1 ; ///<
UINT32 DlStateChanged:1 ; ///<
UINT32 Reserved_31_25:7 ; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x70_STRUCT;
// **** DxF0x74 Register Definition ****
// Address
#define DxF0x74_ADDRESS 0x74
// Type
#define DxF0x74_TYPE TYPE_D4F0
// Field Data
#define DxF0x74_SerrOnCorrErrEn_OFFSET 0
#define DxF0x74_SerrOnCorrErrEn_WIDTH 1
#define DxF0x74_SerrOnCorrErrEn_MASK 0x1
#define DxF0x74_SerrOnNonFatalErrEn_OFFSET 1
#define DxF0x74_SerrOnNonFatalErrEn_WIDTH 1
#define DxF0x74_SerrOnNonFatalErrEn_MASK 0x2
#define DxF0x74_SerrOnFatalErrEn_OFFSET 2
#define DxF0x74_SerrOnFatalErrEn_WIDTH 1
#define DxF0x74_SerrOnFatalErrEn_MASK 0x4
#define DxF0x74_PmIntEn_OFFSET 3
#define DxF0x74_PmIntEn_WIDTH 1
#define DxF0x74_PmIntEn_MASK 0x8
#define DxF0x74_CrsSoftVisibilityEn_OFFSET 4
#define DxF0x74_CrsSoftVisibilityEn_WIDTH 1
#define DxF0x74_CrsSoftVisibilityEn_MASK 0x10
#define DxF0x74_Reserved_15_5_OFFSET 5
#define DxF0x74_Reserved_15_5_WIDTH 11
#define DxF0x74_Reserved_15_5_MASK 0xffe0
#define DxF0x74_CrsSoftVisibility_OFFSET 16
#define DxF0x74_CrsSoftVisibility_WIDTH 1
#define DxF0x74_CrsSoftVisibility_MASK 0x10000
#define DxF0x74_Reserved_31_17_OFFSET 17
#define DxF0x74_Reserved_31_17_WIDTH 15
#define DxF0x74_Reserved_31_17_MASK 0xfffe0000
/// DxF0x74
typedef union {
struct { ///<
UINT32 SerrOnCorrErrEn:1 ; ///<
UINT32 SerrOnNonFatalErrEn:1 ; ///<
UINT32 SerrOnFatalErrEn:1 ; ///<
UINT32 PmIntEn:1 ; ///<
UINT32 CrsSoftVisibilityEn:1 ; ///<
UINT32 Reserved_15_5:11; ///<
UINT32 CrsSoftVisibility:1 ; ///<
UINT32 Reserved_31_17:15; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x74_STRUCT;
// **** DxF0x78 Register Definition ****
// Address
#define DxF0x78_ADDRESS 0x78
// Type
#define DxF0x78_TYPE TYPE_D4F0
// Field Data
#define DxF0x78_PmeRequestorId_OFFSET 0
#define DxF0x78_PmeRequestorId_WIDTH 16
#define DxF0x78_PmeRequestorId_MASK 0xffff
#define DxF0x78_PmeStatus_OFFSET 16
#define DxF0x78_PmeStatus_WIDTH 1
#define DxF0x78_PmeStatus_MASK 0x10000
#define DxF0x78_PmePending_OFFSET 17
#define DxF0x78_PmePending_WIDTH 1
#define DxF0x78_PmePending_MASK 0x20000
#define DxF0x78_Reserved_31_18_OFFSET 18
#define DxF0x78_Reserved_31_18_WIDTH 14
#define DxF0x78_Reserved_31_18_MASK 0xfffc0000
/// DxF0x78
typedef union {
struct { ///<
UINT32 PmeRequestorId:16; ///<
UINT32 PmeStatus:1 ; ///<
UINT32 PmePending:1 ; ///<
UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x78_STRUCT;
// **** DxF0x7C Register Definition ****
// Address
#define DxF0x7C_ADDRESS 0x7c
// Type
#define DxF0x7C_TYPE TYPE_D4F0
// Field Data
#define DxF0x7C_CplTimeoutRangeSup_OFFSET 0
#define DxF0x7C_CplTimeoutRangeSup_WIDTH 4
#define DxF0x7C_CplTimeoutRangeSup_MASK 0xf
#define DxF0x7C_CplTimeoutDisSup_OFFSET 4
#define DxF0x7C_CplTimeoutDisSup_WIDTH 1
#define DxF0x7C_CplTimeoutDisSup_MASK 0x10
#define DxF0x7C_AriForwardingSupported_OFFSET 5
#define DxF0x7C_AriForwardingSupported_WIDTH 1
#define DxF0x7C_AriForwardingSupported_MASK 0x20
#define DxF0x7C_Reserved_31_6_OFFSET 6
#define DxF0x7C_Reserved_31_6_WIDTH 26
#define DxF0x7C_Reserved_31_6_MASK 0xffffffc0
/// DxF0x7C
typedef union {
struct { ///<
UINT32 CplTimeoutRangeSup:4 ; ///<
UINT32 CplTimeoutDisSup:1 ; ///<
UINT32 AriForwardingSupported:1 ; ///<
UINT32 Reserved_31_6:26; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x7C_STRUCT;
// **** DxF0x80 Register Definition ****
// Address
#define DxF0x80_ADDRESS 0x80
// Type
#define DxF0x80_TYPE TYPE_D4F0
// Field Data
#define DxF0x80_CplTimeoutValue_OFFSET 0
#define DxF0x80_CplTimeoutValue_WIDTH 4
#define DxF0x80_CplTimeoutValue_MASK 0xf
#define DxF0x80_CplTimeoutDis_OFFSET 4
#define DxF0x80_CplTimeoutDis_WIDTH 1
#define DxF0x80_CplTimeoutDis_MASK 0x10
#define DxF0x80_AriForwardingEn_OFFSET 5
#define DxF0x80_AriForwardingEn_WIDTH 1
#define DxF0x80_AriForwardingEn_MASK 0x20
#define DxF0x80_Reserved_31_6_OFFSET 6
#define DxF0x80_Reserved_31_6_WIDTH 26
#define DxF0x80_Reserved_31_6_MASK 0xffffffc0
/// DxF0x80
typedef union {
struct { ///<
UINT32 CplTimeoutValue:4 ; ///<
UINT32 CplTimeoutDis:1 ; ///<
UINT32 AriForwardingEn:1 ; ///<
UINT32 Reserved_31_6:26; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x80_STRUCT;
// **** DxF0x84 Register Definition ****
// Address
#define DxF0x84_ADDRESS 0x84
// Type
#define DxF0x84_TYPE TYPE_D4F0
// Field Data
#define DxF0x84_Reserved_31_0_OFFSET 0
#define DxF0x84_Reserved_31_0_WIDTH 32
#define DxF0x84_Reserved_31_0_MASK 0xffffffff
/// DxF0x84
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x84_STRUCT;
// **** DxF0x88 Register Definition ****
// Address
#define DxF0x88_ADDRESS 0x88
// Type
#define DxF0x88_TYPE TYPE_D4F0
// Field Data
#define DxF0x88_TargetLinkSpeed_OFFSET 0
#define DxF0x88_TargetLinkSpeed_WIDTH 4
#define DxF0x88_TargetLinkSpeed_MASK 0xf
#define DxF0x88_EnterCompliance_OFFSET 4
#define DxF0x88_EnterCompliance_WIDTH 1
#define DxF0x88_EnterCompliance_MASK 0x10
#define DxF0x88_HwAutonomousSpeedDisable_OFFSET 5
#define DxF0x88_HwAutonomousSpeedDisable_WIDTH 1
#define DxF0x88_HwAutonomousSpeedDisable_MASK 0x20
#define DxF0x88_SelectableDeemphasis_OFFSET 6
#define DxF0x88_SelectableDeemphasis_WIDTH 1
#define DxF0x88_SelectableDeemphasis_MASK 0x40
#define DxF0x88_XmitMargin_OFFSET 7
#define DxF0x88_XmitMargin_WIDTH 3
#define DxF0x88_XmitMargin_MASK 0x380
#define DxF0x88_EnterModCompliance_OFFSET 10
#define DxF0x88_EnterModCompliance_WIDTH 1
#define DxF0x88_EnterModCompliance_MASK 0x400
#define DxF0x88_ComplianceSOS_OFFSET 11
#define DxF0x88_ComplianceSOS_WIDTH 1
#define DxF0x88_ComplianceSOS_MASK 0x800
#define DxF0x88_ComplianceDeemphasis_OFFSET 12
#define DxF0x88_ComplianceDeemphasis_WIDTH 1
#define DxF0x88_ComplianceDeemphasis_MASK 0x1000
#define DxF0x88_Reserved_15_13_OFFSET 13
#define DxF0x88_Reserved_15_13_WIDTH 3
#define DxF0x88_Reserved_15_13_MASK 0xe000
#define DxF0x88_CurDeemphasisLevel_OFFSET 16
#define DxF0x88_CurDeemphasisLevel_WIDTH 1
#define DxF0x88_CurDeemphasisLevel_MASK 0x10000
#define DxF0x88_Reserved_31_17_OFFSET 17
#define DxF0x88_Reserved_31_17_WIDTH 15
#define DxF0x88_Reserved_31_17_MASK 0xfffe0000
/// DxF0x88
typedef union {
struct { ///<
UINT32 TargetLinkSpeed:4 ; ///<
UINT32 EnterCompliance:1 ; ///<
UINT32 HwAutonomousSpeedDisable:1 ; ///<
UINT32 SelectableDeemphasis:1 ; ///<
UINT32 XmitMargin:3 ; ///<
UINT32 EnterModCompliance:1 ; ///<
UINT32 ComplianceSOS:1 ; ///<
UINT32 ComplianceDeemphasis:1 ; ///<
UINT32 Reserved_15_13:3 ; ///<
UINT32 CurDeemphasisLevel:1 ; ///<
UINT32 Reserved_31_17:15; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x88_STRUCT;
// **** DxF0x8C Register Definition ****
// Address
#define DxF0x8C_ADDRESS 0x8c
// Type
#define DxF0x8C_TYPE TYPE_D4F0
// Field Data
#define DxF0x8C_Reserved_31_0_OFFSET 0
#define DxF0x8C_Reserved_31_0_WIDTH 32
#define DxF0x8C_Reserved_31_0_MASK 0xffffffff
/// DxF0x8C
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x8C_STRUCT;
// **** DxF0x90 Register Definition ****
// Address
#define DxF0x90_ADDRESS 0x90
// Type
#define DxF0x90_TYPE TYPE_D4F0
// Field Data
#define DxF0x90_Reserved_31_0_OFFSET 0
#define DxF0x90_Reserved_31_0_WIDTH 32
#define DxF0x90_Reserved_31_0_MASK 0xffffffff
/// DxF0x90
typedef union {
struct { ///<
UINT32 Reserved_31_0:32; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x90_STRUCT;
// **** DxF0x128 Register Definition ****
// Address
#define DxF0x128_ADDRESS 0x128
// Type
#define DxF0x128_TYPE TYPE_D4F0
// Field Data
#define DxF0x128_Reserved_15_0_OFFSET 0
#define DxF0x128_Reserved_15_0_WIDTH 16
#define DxF0x128_Reserved_15_0_MASK 0xffff
#define DxF0x128_PortArbTableStatus_OFFSET 16
#define DxF0x128_PortArbTableStatus_WIDTH 1
#define DxF0x128_PortArbTableStatus_MASK 0x10000
#define DxF0x128_VcNegotiationPending_OFFSET 17
#define DxF0x128_VcNegotiationPending_WIDTH 1
#define DxF0x128_VcNegotiationPending_MASK 0x20000
#define DxF0x128_Reserved_31_18_OFFSET 18
#define DxF0x128_Reserved_31_18_WIDTH 14
#define DxF0x128_Reserved_31_18_MASK 0xfffc0000
/// DxF0x128
typedef union {
struct { ///<
UINT32 Reserved_15_0:16; ///<
UINT32 PortArbTableStatus:1 ; ///<
UINT32 VcNegotiationPending:1 ; ///<
UINT32 Reserved_31_18:14; ///<
} Field; ///<
UINT32 Value; ///<
} DxF0x128_STRUCT;
// **** D0F0x64_x00 Register Definition ****
// Address
#define D0F0x64_x00_ADDRESS 0x0
// Type
#define D0F0x64_x00_TYPE TYPE_D0F0x64
// Field Data
#define D0F0x64_x00_Reserved_5_0_OFFSET 0
#define D0F0x64_x00_Reserved_5_0_WIDTH 6
#define D0F0x64_x00_Reserved_5_0_MASK 0x3f
#define D0F0x64_x00_NbFchCfgEn_OFFSET 6
#define D0F0x64_x00_NbFchCfgEn_WIDTH 1
#define D0F0x64_x00_NbFchCfgEn_MASK 0x40
#define D0F0x64_x00_HwInitWrLock_OFFSET 7
#define D0F0x64_x00_HwInitWrLock_WIDTH 1
#define D0F0x64_x00_HwInitWrLock_MASK 0x80
#define D0F0x64_x00_Reserved_31_8_OFFSET 8
#define D0F0x64_x00_Reserved_31_8_WIDTH 24
#define D0F0x64_x00_Reserved_31_8_MASK 0xffffff00