mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups
- Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree
- Enable VBT support in Kconfig and add VBT files extracted from
vendor firmware
- Remove IGPU VBIOS entries from Kconfig
- Remove unused PS2 definitions in superio.asl
- Add PWRB ACPI device entry to mainboard.asl
- Remove duplicate chipset register initialization from mainboard.c
- Move ITE Super I/O configuration to mainboard_config_superio in
romstage.c
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
index 6869bdb..af884f6 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
@@ -12,6 +12,7 @@
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
+ select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_LIBGFXINIT
@@ -37,12 +38,4 @@
int
default 8
-config VGA_BIOS_ID
- string
- default "8086,0162"
-
-config VGA_BIOS_FILE
- string
- default "pci8086,0162.rom"
-
endif # BOARD_GIGABYTE_GA_B75M_D3H
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl
index 34de86f..a1c7989 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl
@@ -18,6 +18,6 @@
{
Device (PWRB)
{
- Name (_HID, EisaId("PNP0C0C"))
+ Name (_HID, EisaId ("PNP0C0C"))
}
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl
index 0603164..10856d3 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl
@@ -17,14 +17,13 @@
* entering a sleep state. The sleep state number is passed in Arg0
*/
-Method(_PTS,1)
+Method (_PTS, 1)
{
-
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
- Return(Package(){0,0})
+ Return (Package () {0, 0})
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl
index 78bf687..e69de29 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* mainboard configuration */
-
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt
index 7ee7f95..c4fb591 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt
@@ -1,5 +1,5 @@
Category: desktop
-Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp
+Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4150#ov
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt b/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt
new file mode 100644
index 0000000..ccbf6ee
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/data.vbt
Binary files differ
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
index 7a3568a..ceb9279 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
@@ -21,16 +21,15 @@
device domain 0 on
subsystemid 0x1458 0x5000 inherit
- device pci 00.0 on # host bridge
+ device pci 00.0 on # Host bridge
subsystemid 0x1458 0x5000
end
device pci 01.0 on end # PCIe Bridge for discrete graphics
- device pci 02.0 on # vga controller
+ device pci 02.0 on # Integrated VGA controller
subsystemid 0x1458 0xd000
end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
-
# GPI routing
register "alt_gp_smi_en" = "0x0000"
register "gen1_dec" = "0x003c0a01"
@@ -109,7 +108,7 @@
end
chip drivers/pc80/tpm
- device pnp 0c31.0 on end
+ device pnp 0c31.0 on end
end
end
device pci 1f.2 on # SATA Controller 1
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
index 67054cc..c00ee30 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
@@ -24,7 +24,9 @@
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
// Some generic macros
+ #include "acpi/mainboard.asl"
#include "acpi/platform.asl"
+ #include "acpi/thermal.asl"
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
index 4e8d9f5..cc26757 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
@@ -19,54 +19,16 @@
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
-static void mainboard_init(struct device *dev)
-{
- RCBA32(0x38c8) = 0x00002005;
- RCBA32(0x38c4) = 0x00802005;
- RCBA32(0x2240) = 0x00330e71;
- RCBA32(0x2244) = 0x003f0eb1;
- RCBA32(0x2248) = 0x002102cd;
- RCBA32(0x224c) = 0x00f60000;
- RCBA32(0x2250) = 0x00020000;
- RCBA32(0x2254) = 0x00e3004c;
- RCBA32(0x2258) = 0x00e20bef;
- RCBA32(0x2260) = 0x003304ed;
- RCBA32(0x2278) = 0x001107c1;
- RCBA32(0x227c) = 0x001d07e9;
- RCBA32(0x2280) = 0x00e20000;
- RCBA32(0x2284) = 0x00ee0000;
- RCBA32(0x2288) = 0x005b05d3;
- RCBA32(0x2318) = 0x04b8ff2e;
- RCBA32(0x231c) = 0x03930f2e;
- RCBA32(0x3808) = 0x005044a3;
- RCBA32(0x3810) = 0x52410000;
- RCBA32(0x3814) = 0x0000008a;
- RCBA32(0x3818) = 0x00000006;
- RCBA32(0x381c) = 0x0000072e;
- RCBA32(0x3820) = 0x0000000a;
- RCBA32(0x3824) = 0x00000123;
- RCBA32(0x3828) = 0x00000009;
- RCBA32(0x382c) = 0x00000001;
- RCBA32(0x3834) = 0x0000061a;
- RCBA32(0x3838) = 0x00000003;
- RCBA32(0x383c) = 0x00000a76;
- RCBA32(0x3840) = 0x00000004;
- RCBA32(0x3844) = 0x0000e5e4;
- RCBA32(0x3848) = 0x0000000e;
-}
-
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(struct device *dev)
{
- dev->ops->init = mainboard_init;
-
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
- GMA_INT15_BOOT_DISPLAY_CRT, 0);
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
+ .enable_dev = mainboard_enable
};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index aa5f484..4964785 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -25,12 +25,6 @@
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
-void mainboard_rcba_config(void)
-{
- /* Enable HECI */
- RCBA32(FD2) &= ~0x2;
-}
-
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
@@ -40,7 +34,10 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
+}
+void mainboard_config_superio(void)
+{
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -87,18 +84,20 @@
{ 1, 5, 6 },
};
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd (&spd[0], 0x50, id_only);
- read_spd (&spd[1], 0x51, id_only);
- read_spd (&spd[2], 0x52, id_only);
- read_spd (&spd[3], 0x53, id_only);
-}
-
void mainboard_early_init(int s3resume)
{
}
-void mainboard_config_superio(void)
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+void mainboard_rcba_config(void)
+{
+ /* Enable HECI */
+ RCBA32(FD2) &= ~0x2;
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
index 4048f98..d86c742 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
@@ -12,9 +12,11 @@
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
+ select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_LPC_TPM
config DRAM_RESET_GATE_GPIO
int
@@ -36,12 +38,4 @@
int
default 8
-config VGA_BIOS_ID
- string
- default "8086,0102"
-
-config VGA_BIOS_FILE
- string
- default "pci8086,0102.rom"
-
endif # BOARD_GIGABYTE_GA_B75M_D3V
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
new file mode 100644
index 0000000..a1c7989
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
index d8d3320..10856d3 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
@@ -17,7 +17,7 @@
* entering a sleep state. The sleep state number is passed in Arg0
*/
-Method(_PTS,1)
+Method (_PTS, 1)
{
}
@@ -25,5 +25,5 @@
Method(_WAK,1)
{
- Return(Package(){0,0})
+ Return (Package () {0, 0})
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
index 4c50b6c..e69de29 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
@@ -1,4 +0,0 @@
-/* mainboard configuration */
-
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
index ede1945..5535d9a 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
@@ -1,7 +1,7 @@
Category: desktop
-Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov
+Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4151#ov
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
-Release date: 2012
+Release year: 2012
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt b/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt
new file mode 100644
index 0000000..ccbf6ee
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/data.vbt
Binary files differ
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
index a00e2ee..ceb9279 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
@@ -1,4 +1,5 @@
chip northbridge/intel/sandybridge
+ # IGD Displays
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
@@ -20,16 +21,15 @@
device domain 0 on
subsystemid 0x1458 0x5000 inherit
- device pci 00.0 on # host bridge
+ device pci 00.0 on # Host bridge
subsystemid 0x1458 0x5000
end
device pci 01.0 on end # PCIe Bridge for discrete graphics
- device pci 02.0 on # vga controller
+ device pci 02.0 on # Integrated VGA controller
subsystemid 0x1458 0xd000
end
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
-
# GPI routing
register "alt_gp_smi_en" = "0x0000"
register "gen1_dec" = "0x003c0a01"
@@ -106,6 +106,10 @@
device pnp 2e.7 off end # GPIO
device pnp 2e.a off end # IR
end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
end
device pci 1f.2 on # SATA Controller 1
subsystemid 0x1458 0xb005
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
index 67054cc..c00ee30 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
@@ -24,7 +24,9 @@
#include <southbridge/intel/bd82x6x/acpi/platform.asl>
// Some generic macros
+ #include "acpi/mainboard.asl"
#include "acpi/platform.asl"
+ #include "acpi/thermal.asl"
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
index 4e8d9f5..cc26757 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
@@ -19,54 +19,16 @@
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>
-static void mainboard_init(struct device *dev)
-{
- RCBA32(0x38c8) = 0x00002005;
- RCBA32(0x38c4) = 0x00802005;
- RCBA32(0x2240) = 0x00330e71;
- RCBA32(0x2244) = 0x003f0eb1;
- RCBA32(0x2248) = 0x002102cd;
- RCBA32(0x224c) = 0x00f60000;
- RCBA32(0x2250) = 0x00020000;
- RCBA32(0x2254) = 0x00e3004c;
- RCBA32(0x2258) = 0x00e20bef;
- RCBA32(0x2260) = 0x003304ed;
- RCBA32(0x2278) = 0x001107c1;
- RCBA32(0x227c) = 0x001d07e9;
- RCBA32(0x2280) = 0x00e20000;
- RCBA32(0x2284) = 0x00ee0000;
- RCBA32(0x2288) = 0x005b05d3;
- RCBA32(0x2318) = 0x04b8ff2e;
- RCBA32(0x231c) = 0x03930f2e;
- RCBA32(0x3808) = 0x005044a3;
- RCBA32(0x3810) = 0x52410000;
- RCBA32(0x3814) = 0x0000008a;
- RCBA32(0x3818) = 0x00000006;
- RCBA32(0x381c) = 0x0000072e;
- RCBA32(0x3820) = 0x0000000a;
- RCBA32(0x3824) = 0x00000123;
- RCBA32(0x3828) = 0x00000009;
- RCBA32(0x382c) = 0x00000001;
- RCBA32(0x3834) = 0x0000061a;
- RCBA32(0x3838) = 0x00000003;
- RCBA32(0x383c) = 0x00000a76;
- RCBA32(0x3840) = 0x00000004;
- RCBA32(0x3844) = 0x0000e5e4;
- RCBA32(0x3848) = 0x0000000e;
-}
-
// mainboard_enable is executed as first thing after
// enumerate_buses().
static void mainboard_enable(struct device *dev)
{
- dev->ops->init = mainboard_init;
-
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
- GMA_INT15_BOOT_DISPLAY_CRT, 0);
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
+ .enable_dev = mainboard_enable
};
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 035e20e..eb88d36 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -25,12 +25,6 @@
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
-void mainboard_rcba_config(void)
-{
- /* Enable HECI */
- RCBA32(FD2) &= ~0x2;
-}
-
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
@@ -40,7 +34,10 @@
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
+}
+void mainboard_config_superio(void)
+{
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -87,19 +84,21 @@
{ 1, 5, 6 },
};
-/* FIXME: This board only has two DIMM slots! */
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd (&spd[0], 0x50, id_only);
- read_spd (&spd[1], 0x51, id_only);
- read_spd (&spd[2], 0x52, id_only);
- read_spd (&spd[3], 0x53, id_only);
-}
-
void mainboard_early_init(int s3resume)
{
}
-void mainboard_config_superio(void)
+/* FIXME: This board only has two DIMM slots! */
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
+
+void mainboard_rcba_config(void)
+{
+ /* Enable HECI */
+ RCBA32(FD2) &= ~0x2;
}