tree 3284e241bccdc5e6ba27f32b75c02f97ee8c30a4
parent dd20d5d36cc5350e834cad4052d9376bd29928a1
author Kein Yuan <kein.yuan@intel.com> 1396649714 -0700
committer Marc Jones <marc.jones@se-eng.com> 1414516134 +0100

rambi: switch MCLK from 19.2Mhz to 25Mhz

With following settings
    1.Coreboot 25Mhz
    2.Maxim codec configured with MCLK=25Mhz
    2.I2C 400Khz fixed
    4.Including  Enable/Disable SHDN bit when LRCLK starts/Stops
    5.Removed PLL toggle workaround routine.
audio playing is smooth before/after S3, no noise when recording so change
MCLK from 19.2 back to 25Mhz.

BUG=chrome-os-partner:26948
BRANCH=firmware-rambi-5216
TEST=test audio play and record on Rambi, works fine.

Change-Id: I5602feb39721344feab837ff4a3a18309a47a6a6
Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/193881
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit bfe1d535aa2f20a32e163abeb99f3d657e2b43ab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7219
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)