soc/amd/stoneyridge: move northbridge ops to northbridge device
The northbridge ops should be added to the actual northbridge and not
the first HT device. Neither of the devices has BARs on it, so
read_resources implementation will still work correctly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e5f21bfe5fff043d7d9afafa360764203dd61f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68409
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/stoneyridge/chipset_st.cb b/src/soc/amd/stoneyridge/chipset_st.cb
index be630d9..3544ea8 100644
--- a/src/soc/amd/stoneyridge/chipset_st.cb
+++ b/src/soc/amd/stoneyridge/chipset_st.cb
@@ -6,7 +6,7 @@
end
device domain 0 on
ops stoneyridge_pci_domain_ops
- device pci 00.0 alias gnb on end
+ device pci 00.0 alias gnb on ops stoneyridge_northbridge_operations end
device pci 00.2 alias iommu off end
device pci 01.0 alias gfx off end # internal GPU
device pci 01.1 alias gfx_hda off end # display HD Audio controller
@@ -25,7 +25,7 @@
device pci 14.0 alias smbus on end # primary FCH function
device pci 14.3 alias lpc_bridge on end
device pci 14.7 alias sdhci off end
- device pci 18.0 alias ht_0 on ops stoneyridge_northbridge_operations end
+ device pci 18.0 alias ht_0 on end
device pci 18.1 alias ht_1 on end
device pci 18.2 alias ht_2 on end
device pci 18.3 alias ht_3 on end