commit 251279c537397835a4504165e7582cb29c19891c
author Elyes HAOUAS <ehaouas@noos.fr> Sun Jul 08 12:41:56 2018 +0200
committer Patrick Georgi <pgeorgi@google.com> Mon Jul 09 09:31:54 2018 +0000
tree a4d208e75433392f19b18b912ecf642b7a545ba4
parent 39303d5d4960814fc606cce3a9ec10545faaef4b

src/southbridge: Use "foo *bar" instead of "foo* bar"

Change-Id: I72d50615d77b91529810e8f590fa56f3c6f7546c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/southbridge/amd/common/amd_pci_util.c

diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index 2acd151..ca76809 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -26,8 +26,8 @@
 
 const struct pirq_struct * pirq_data_ptr = NULL;
 u32 pirq_data_size = 0;
-const u8 * intr_data_ptr = NULL;
-const u8 * picr_data_ptr = NULL;
+const u8 *intr_data_ptr = NULL;
+const u8 *picr_data_ptr = NULL;
 
 /*
  * Read the FCH PCI_INTR registers 0xC00/0xC01 at a