veyron: Trigger hard reset (via GPIO) if last reboot was caused by watchdog
Like Nyan, Veyron boards use a GPIO to reset the system so that we can
make the accompanying TPM reset secure and unforgeable. The normal
kernel reboot driver knows that, but the SoC-internal watchdog doesn't.
This patch implements a check for the global reset status register in
the early bootblock and triggers a hard_reset() when it matches "first
global watchdog reset" or "second global watchdog reset". Seems that
the difference between the two is is a choice controlled by
wdt_glb_srst_ctrl (unconfirmed), and we want this code to run in both
cases.
BRANCH=None
BUG=chrome-os-partner:33141
TEST=Run 'mem w 0xff800000 0x9' from the command line, watch how you end
up in recovery without this patch but can boot normally with it.
Change-Id: Ice79648831e1e97d22325711da9e82bbf6bf3c75
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 5d7cb52b2c2dcb2fff0bf83fc168439dade4b1b7
Original-Change-Id: I2581bde84f0445c15896060544e9acb60de91c8c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231734
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9629
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
diff --git a/src/mainboard/google/veyron_jerry/bootblock.c b/src/mainboard/google/veyron_jerry/bootblock.c
index 1e46ed0..4536f31 100644
--- a/src/mainboard/google/veyron_jerry/bootblock.c
+++ b/src/mainboard/google/veyron_jerry/bootblock.c
@@ -21,7 +21,9 @@
#include <arch/io.h>
#include <assert.h>
#include <bootblock_common.h>
+#include <console/console.h>
#include <delay.h>
+#include <reset.h>
#include <soc/clock.h>
#include <soc/i2c.h>
#include <soc/grf.h>
@@ -55,6 +57,11 @@
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
+ if (rkclk_was_watchdog_reset()) {
+ printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+ hard_reset();
+ }
+
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_mighty/bootblock.c b/src/mainboard/google/veyron_mighty/bootblock.c
index 1e46ed0..4536f31 100644
--- a/src/mainboard/google/veyron_mighty/bootblock.c
+++ b/src/mainboard/google/veyron_mighty/bootblock.c
@@ -21,7 +21,9 @@
#include <arch/io.h>
#include <assert.h>
#include <bootblock_common.h>
+#include <console/console.h>
#include <delay.h>
+#include <reset.h>
#include <soc/clock.h>
#include <soc/i2c.h>
#include <soc/grf.h>
@@ -55,6 +57,11 @@
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
+ if (rkclk_was_watchdog_reset()) {
+ printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+ hard_reset();
+ }
+
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_pinky/bootblock.c b/src/mainboard/google/veyron_pinky/bootblock.c
index 1e46ed0..4536f31 100644
--- a/src/mainboard/google/veyron_pinky/bootblock.c
+++ b/src/mainboard/google/veyron_pinky/bootblock.c
@@ -21,7 +21,9 @@
#include <arch/io.h>
#include <assert.h>
#include <bootblock_common.h>
+#include <console/console.h>
#include <delay.h>
+#include <reset.h>
#include <soc/clock.h>
#include <soc/i2c.h>
#include <soc/grf.h>
@@ -55,6 +57,11 @@
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
+ if (rkclk_was_watchdog_reset()) {
+ printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+ hard_reset();
+ }
+
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/mainboard/google/veyron_speedy/bootblock.c b/src/mainboard/google/veyron_speedy/bootblock.c
index 1e46ed0..4536f31 100644
--- a/src/mainboard/google/veyron_speedy/bootblock.c
+++ b/src/mainboard/google/veyron_speedy/bootblock.c
@@ -21,7 +21,9 @@
#include <arch/io.h>
#include <assert.h>
#include <bootblock_common.h>
+#include <console/console.h>
#include <delay.h>
+#include <reset.h>
#include <soc/clock.h>
#include <soc/i2c.h>
#include <soc/grf.h>
@@ -55,6 +57,11 @@
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
+ if (rkclk_was_watchdog_reset()) {
+ printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n");
+ hard_reset();
+ }
+
/* i2c1 for tpm */
writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index fe42910..ab12e8c 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -640,3 +640,9 @@
}
return 0;
}
+
+int rkclk_was_watchdog_reset(void)
+{
+ /* Bits 5 and 4 are "second" and "first" global watchdog reset. */
+ return readl(&cru_ptr->cru_glb_rst_st) & 0x30;
+}
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index b8f892b..cbf4ba0 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -49,4 +49,5 @@
void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz);
void rkclk_configure_edp(void);
+int rkclk_was_watchdog_reset(void);
#endif /* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */