diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h
index a50aec9..8e6222c 100644
--- a/src/soc/intel/alderlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_ALDERLAKE_GPIO_DEFS_H_
 #define _SOC_ALDERLAKE_GPIO_DEFS_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h b/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h
index a2ab413..1fc3cda 100644
--- a/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h
+++ b/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_ALDERLAKE_GPIO_DEFS_PCH_S_H_
 #define _SOC_ALDERLAKE_GPIO_DEFS_PCH_S_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs_pch_s.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h
index 3a22d25..679d538 100644
--- a/src/soc/intel/alderlake/include/soc/romstage.h
+++ b/src/soc/intel/alderlake/include/soc/romstage.h
@@ -4,7 +4,6 @@
 #define _SOC_ROMSTAGE_H_
 
 #include <fsp/api.h>
-#include <stddef.h>
 
 void mainboard_memory_init_params(FSPM_UPD *memupd);
 void systemagent_early_init(void);
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 2ee078d..17fb7d5 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_CANNONLAKE_GPIO_DEFS_H_
 #define _SOC_CANNONLAKE_GPIO_DEFS_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
index 4f87459..6e9e2b0 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs_cnp_h.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_
 #define _SOC_CANNONLAKE_GPIO_DEFS_CNP_H_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs_cnp_h.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/common/block/include/intelblocks/p2sblib.h b/src/soc/intel/common/block/include/intelblocks/p2sblib.h
index 9f6b97d..122e790 100644
--- a/src/soc/intel/common/block/include/intelblocks/p2sblib.h
+++ b/src/soc/intel/common/block/include/intelblocks/p2sblib.h
@@ -3,7 +3,6 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_P2SBLIB_H
 #define SOC_INTEL_COMMON_BLOCK_P2SBLIB_H
 
-#include <stddef.h>
 #include <stdint.h>
 
 /* P2SB generic configuration register */
diff --git a/src/soc/intel/elkhartlake/include/soc/gpio_defs.h b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h
index 61d7f6a..ef7c6c5 100644
--- a/src/soc/intel/elkhartlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/elkhartlake/include/soc/gpio_defs.h
@@ -3,12 +3,8 @@
 #ifndef _SOC_ELKHARTLAKE_GPIO_DEFS_H_
 #define _SOC_ELKHARTLAKE_GPIO_DEFS_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs.h>
 
-
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
 
 #define NUM_GPIO_COMx_GPI_REGS(n)	\
diff --git a/src/soc/intel/jasperlake/include/soc/gpio_defs.h b/src/soc/intel/jasperlake/include/soc/gpio_defs.h
index 51ef531..8f6f5f7 100644
--- a/src/soc/intel/jasperlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/jasperlake/include/soc/gpio_defs.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_JASPERLAKE_GPIO_DEFS_H_
 #define _SOC_JASPERLAKE_GPIO_DEFS_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/meteorlake/include/soc/gpio_defs.h b/src/soc/intel/meteorlake/include/soc/gpio_defs.h
index 8b5d2d9..ca2e8dd 100644
--- a/src/soc/intel/meteorlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/meteorlake/include/soc/gpio_defs.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_METEORLAKE_GPIO_DEFS_H_
 #define _SOC_METEORLAKE_GPIO_DEFS_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs.h>
 
 #define GPIO_NUM_PAD_CFG_REGS	4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/meteorlake/include/soc/romstage.h b/src/soc/intel/meteorlake/include/soc/romstage.h
index b9b3cf8..2eaa84b 100644
--- a/src/soc/intel/meteorlake/include/soc/romstage.h
+++ b/src/soc/intel/meteorlake/include/soc/romstage.h
@@ -4,7 +4,6 @@
 #define _SOC_ROMSTAGE_H_
 
 #include <fsp/api.h>
-#include <stddef.h>
 #include <soc/soc_chip.h>
 
 void mainboard_update_premem_soc_chip_config(struct soc_intel_meteorlake_config *config);
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index de14bb6..0e98b89 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -2,9 +2,7 @@
 
 #ifndef _SOC_GPIO_DEFS_H_
 #define _SOC_GPIO_DEFS_H_
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
+
 #if CONFIG(SKYLAKE_SOC_PCH_H)
 # include <soc/gpio_pch_h_defs.h>
 #else
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
index f58fb55..57eeaf3 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_TIGERLAKE_GPIO_DEFS_H_
 #define _SOC_TIGERLAKE_GPIO_DEFS_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h b/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h
index 1a9b2f3..abf99b8 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_defs_pch_h.h
@@ -3,9 +3,6 @@
 #ifndef _SOC_TIGERLAKE_GPIO_DEFS_PCH_H_H_
 #define _SOC_TIGERLAKE_GPIO_DEFS_PCH_H_H_
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
 #include <soc/gpio_soc_defs_pch_h.h>
 
 #define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */
diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/gpio_soc_defs.h b/src/soc/intel/xeon_sp/lbg/include/soc/gpio_soc_defs.h
index 6f3ddcd..5208256 100644
--- a/src/soc/intel/xeon_sp/lbg/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/xeon_sp/lbg/include/soc/gpio_soc_defs.h
@@ -3,10 +3,6 @@
 #ifndef LEWISBURG_GPIO_DEFS_H
 #define LEWISBURG_GPIO_DEFS_H
 
-#ifndef __ACPI__
-#include <stddef.h>
-#endif
-
 /* GPIO Community 0 */
 #define COMM_0			0
 #define  GPP_A			0x0