commit 2421de6701565269d1e10845e487a588abb8fc40
author Felix Held <felix-coreboot@felixheld.de> Fri Mar 26 01:13:53 2021 +0100
committer Felix Held <felix-coreboot@felixheld.de> Mon Mar 29 19:52:22 2021 +0000
tree 6e747070c58e4d92906c242d9dc21e48423282b6
parent dd737142490828c3aa2244216a2fda6df26a4c47

soc/amd/cezanne: factor out UPD-M configuration from romstage

Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f7f5879ac318372042ff703ebbe584ce1c32c91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/cezanne/Makefile.inc

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index dfa047f..80ce622 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -21,6 +21,7 @@
 verstage_x86-y	+= reset.c
 verstage_x86-y	+= uart.c
 
+romstage-y	+= fsp_m_params.c
 romstage-y	+= i2c.c
 romstage-y	+= gpio.c
 romstage-y	+= reset.c

src/soc/amd/cezanne/fsp_m_params.c

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
new file mode 100644
index 0000000..cb60c89
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/apob_cache.h>
+#include <amdblocks/memmap.h>
+#include <console/uart.h>
+#include <fsp/api.h>
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
+
+	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
+
+	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
+	mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
+	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
+	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
+	mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
+	mcfg->serial_port_baudrate = get_uart_baudrate();
+	mcfg->serial_port_refclk = uart_platform_refclk();
+}

src/soc/amd/cezanne/romstage.c

diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 17c7d75..643b067 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -6,26 +6,9 @@
 #include <amdblocks/memmap.h>
 #include <arch/cpu.h>
 #include <console/console.h>
-#include <console/uart.h>
 #include <fsp/api.h>
 #include <program_loading.h>
 
-void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
-{
-	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
-
-	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
-
-	mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
-	mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
-	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
-	mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
-	mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
-	mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
-	mcfg->serial_port_baudrate = get_uart_baudrate();
-	mcfg->serial_port_refclk = uart_platform_refclk();
-}
-
 asmlinkage void car_stage_entry(void)
 {
 	post_code(0x40);