Add support for the Intel Atom D400/500- and N400-series integrated
northbridge. Also add support for the very similar Q963/965 northbridge.
Tested:
D510: confirmed working, with MCHBAR enable code
Q965: writes to bit 0 to enable MCHBAR access are ignored, all other functions work
Untested:
D410/D525/N400: should be the same northbridge
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 236f8c8..2b066b1 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -41,12 +41,15 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index e9a9beb..01323d8 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -62,6 +62,7 @@
#define PCI_DEVICE_ID_INTEL_82945P 0x2770
#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
+#define PCI_DEVICE_ID_INTEL_Q965 0x2990
#define PCI_DEVICE_ID_INTEL_82975X 0x277c
#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
@@ -69,6 +70,10 @@
#define PCI_DEVICE_ID_INTEL_GS45 0x2a40
#define PCI_DEVICE_ID_INTEL_X58 0x3405
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
+#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
+
+/* untested, but almost identical to D-series */
+#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c
index 5c25dd0..a076876 100644
--- a/util/inteltool/memory.c
+++ b/util/inteltool/memory.c
@@ -47,6 +47,31 @@
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
break;
+ case PCI_DEVICE_ID_INTEL_Q965:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
+ mchbar_phys = pci_read_long(nb, 0x48);
+
+ /* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
+ * If it isn't, try to set it. This may fail, because there is
+ * some bit that locks that bit, and isn't in the public
+ * datasheets.
+ */
+
+ if(!(mchbar_phys & 1))
+ {
+ printf("Access to the MCHBAR is currently disabled, "\
+ "attempting to enable.\n");
+ mchbar_phys |= 0x1;
+ pci_write_long(nb, 0x48, mchbar_phys);
+ if(pci_read_long(nb, 0x48) & 1)
+ printf("Enabled successfully.\n");
+ else
+ printf("Enable FAILED!\n");
+ }
+ mchbar_phys &= 0xfffffffe;
+ mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
+ break;
case PCI_DEVICE_ID_INTEL_82443LX:
case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810:
diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c
index 771a28f..10b79e4 100644
--- a/util/inteltool/pcie.c
+++ b/util/inteltool/pcie.c
@@ -40,10 +40,13 @@
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_PM965:
+ case PCI_DEVICE_ID_INTEL_Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break;
@@ -94,10 +97,13 @@
dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_PM965:
+ case PCI_DEVICE_ID_INTEL_Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
break;
@@ -149,10 +155,13 @@
pciexbar_reg = pci_read_long(nb, 0x48);
break;
case PCI_DEVICE_ID_INTEL_PM965:
+ case PCI_DEVICE_ID_INTEL_Q965:
case PCI_DEVICE_ID_INTEL_82Q35:
case PCI_DEVICE_ID_INTEL_82G33:
case PCI_DEVICE_ID_INTEL_82Q33:
case PCI_DEVICE_ID_INTEL_GS45:
+ case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
+ case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break;