soc/intel/meteorlake: Refactor bootblock SoC programming code

This patch ensures the IP initialization being done as part of MTL
bootblock code is able to complete the bootblock phase without any
visible hang.

The re-ordering in the MTL bootblock SoC programming is required to
ensure the SA early initialization is taking place prior to
performing any PCI Read/Write operation (like P2SB bar enabling for
IOE die etc.).

Additionally, Fast SPI init takes place prior to enabling ROM caching
etc.

BUG=b:224325352
TEST= Able to build and start booting the MTL simics.
Without this change, the code execution is stuck as below:

[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC
[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[ERROR]  init_vbnv: failed to locate NVRAM
[EMERG]  Cannot locate primary CBFS

Able to detect the Flash and reading the SPI flash layout in proper
with this change as below:
[NOTE ]  coreboot-4.16-1236-g856464f162-dirty Sun May 29 15:32:20 UTC 2022 bootblock starting (log level: 8)
[DEBUG]  CPU: Intel(R) Core(TM) i7 CPU (server)     @ 2.00GHz
[DEBUG]  CPU: ID a06a0, MeteorLake A0, ucode: 80000018
[DEBUG]  CPU: AES supported, TXT supported, VT supported
[DEBUG]  MCH: device id 7d02 (rev 00) is MeteorLake P
[DEBUG]  PCH: device id 7e01 (rev 00) is MeteorLake SOC␛␛[DEBUG]  IGD: device id ffff (rev ff) is Unknown
[INFO ]  PMC: Using default GPE route.
[INFO ]  VBNV: CMOS invalid, restoring from flash
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x1804000.
[DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 33
[DEBUG]  FMAP: area RW_NVRAM found @ 112b000 (24576 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8485b195f77225d8870589ff2e4d3dbdc8931f0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2 files changed
tree: c21d4b5d95877ec0f93056eb76bf84f4aafa580a
  1. 3rdparty/
  2. configs/
  3. Documentation/
  4. LICENSES/
  5. payloads/
  6. spd/
  7. src/
  8. tests/
  9. util/
  10. .checkpatch.conf
  11. .clang-format
  12. .editorconfig
  13. .gitignore
  14. .gitmodules
  15. .gitreview
  16. .mailmap
  17. AUTHORS
  18. COPYING
  19. gnat.adc
  20. MAINTAINERS
  21. Makefile
  22. Makefile.inc
  23. README.md
  24. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.