commit 23836e2345282151b0b46de6cdcd2bb2faee87f6
author Stefan Reinauer <stepan@coresystems.de> Thu Apr 15 12:39:29 2010 +0000
committer Stefan Reinauer <stepan@openbios.org> Thu Apr 15 12:39:29 2010 +0000
tree e1e416ae11a78b455a26f378f33d0a8db6fa69af
parent c30a6e859e20dbadbad006f2f93068e7f9c36043

zero warnings days...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/supermicro/h8dmr/romstage.c

diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 3dc8e30..28332dc 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -80,10 +80,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -99,12 +95,9 @@
 }
 
 #include "northbridge/amd/amdk8/amdk8_f.h"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-
+#include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/raminit_f.c"
-
 #include "lib/generic_sdram.c"
 
 #include "resourcemap.c" 
@@ -120,8 +113,6 @@
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
 #include "cpu/amd/model_fxx/init_cpus.c"
@@ -263,8 +254,6 @@
 
 //        enable_smbus(); /* enable in sio_setup */
 
-        memreset_setup();
-
         //do we need apci timer, tsc...., only debug need it for better output
         /* all ap stopped? */
 //        init_timer(); // Need to use TMICT to synconize FID/VID
@@ -272,6 +261,4 @@
         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 
         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
 }
-