| commit | 22d6ee8d9cda51d20ca4173593b9574f7dac65ff | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Mon Nov 07 10:03:40 2022 +0100 |
| committer | Arthur Heymans <arthur@aheymans.xyz> | Thu Dec 01 10:28:03 2022 +0000 |
| tree | 9b672418bce3536132eceff8a288d0ef7340e1ed | |
| parent | 2fb6f68ef09358aa6f2550519e71a1d74702d5ef [diff] [blame] |
nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..28af26f 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -3,6 +3,7 @@ chip northbridge/intel/i945 device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -14,6 +15,7 @@ register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on # host bridge subsystemid 0x1458 0x5000 end