tree f66f82134f87bd6d91dfcabb2b5e18aebe6691d2
parent c3c7f8fc60eea829a8cf5e3b02cf7de9cd7c5792
author Felix Held <felix-coreboot@felixheld.de> 1616420698 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1616530139 +0000

soc/amd/cezanne: select HAVE_EM100_SUPPORT

This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>