x86: Add ramstage CBFS cache scratchpad support
Having a CBFS cache scratchpad offers a generic way to decompress CBFS
files through the cbfs_map() function without having to reserve a
per-file specific memory region.
This commit introduces the x86 `RAMSTAGE_CBFS_CACHE_SIZE' Kconfig to
set a ramstage CBFS cache size. A cache size of zero disables the
CBFS cache feature. The default size is 16 KB which seems a
reasonable minimal value large enough to satisfy basic needs such as
the decompression of a small configuration file. This setting can be
adjusted depending on the platform needs and capabilities.
To support S3 suspend/resume use-case, the CBFS cache memory cannot be
released to the operating system. There are two options to meet this
requirement:
1. Define a static CBFS cache buffer (located in the .bss section)
2. Create a new CBMEM entry
Option #2 seems more powerful but considering that:
1. The CBFS cache is actually not a cache but just a scratch pad
designed to be isolated between stages
2. postcar is a very short stage not really needing CBFS cache
3. The static initialization of the `cbfs_cache' global
variable (cf. src/lib/cbfs.c) offers a simple and robust design
=> It is simpler to use a static buffer and limit the support to
ramstage.
Since some AMD SoCs (cf. `SOC_AMD_COMMON_BLOCK_NONCAR' Kconfig) define
a `_cbfs_cache' region, an extra `POSTRAM_CBFS_CACHE_IN_BSS' Kconfig
must be set to enable the use of a static buffer as the CBFS cache
scratchpad.
TEST=Decompression of vbt.bin in ramstage on rex using cbfs_map()
Change-Id: I7fbb1b51cda9f84842992e365b16c5ced1010b89
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77885
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index b0e479b..90ece988 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -160,6 +160,23 @@
Define the size of the Pre-RAM stages CBFS cache. A size of
zero disables the CBFS cache feature in pre-memory stages.
+config POSTRAM_CBFS_CACHE_IN_BSS
+ bool
+ default y if !SOC_AMD_COMMON_BLOCK_NONCAR
+ help
+ Allocate the post-memory CBFS cache scratchpad in the .bss
+ section. CBFS cache will rely on a simple static C buffer
+ while traditionally CBFS cache memory region is reserved in
+ the device memory layout.
+
+config RAMSTAGE_CBFS_CACHE_SIZE
+ hex
+ default 0x4000
+ depends on POSTRAM_CBFS_CACHE_IN_BSS
+ help
+ Define the size of the ramstage CBFS cache. A size of zero
+ disables the CBFS cache feature in ramstage.
+
config PC80_SYSTEM
bool
default y if ARCH_X86
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 8c3db4b..1663517 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -20,8 +20,16 @@
#include <thread.h>
#include <timestamp.h>
+#if ENV_X86 && (ENV_POSTCAR || ENV_SMM)
+struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0);
+#elif CONFIG(POSTRAM_CBFS_CACHE_IN_BSS) && ENV_RAMSTAGE
+static u8 cache_buffer[CONFIG_RAMSTAGE_CBFS_CACHE_SIZE];
+struct mem_pool cbfs_cache =
+ MEM_POOL_INIT(cache_buffer, sizeof(cache_buffer), CONFIG_CBFS_CACHE_ALIGN);
+#else
struct mem_pool cbfs_cache =
MEM_POOL_INIT(_cbfs_cache, REGION_SIZE(cbfs_cache), CONFIG_CBFS_CACHE_ALIGN);
+#endif
static void switch_to_postram_cache(int unused)
{