commit 221fdd8cce708f192a457f39a703e9a968b2f847
author Julius Werner <jwerner@chromium.org> Tue Jun 07 15:44:39 2016 -0700
committer Julius Werner <jwerner@chromium.org> Wed Jun 08 23:21:18 2016 +0200
tree 3c3e4cf751e07bce323d6cfe80901f03e0db92ce
parent 5554d1cf8a4209fa844ae487438030006623d702

veyron: Add exception_init() to romstage

I'm not even sure how this slipped through... looks like it had never
been there in the first place. Anyway, on ARM exceptions should always
be reinitialized in all stages to make sure the handlers are still
around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one).

Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/google/veyron/romstage.c

diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index c5b3a57..bacbeca 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -84,6 +84,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();
 

src/mainboard/google/veyron_brain/romstage.c

diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
index 8b5b660..1c139f1 100644
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ b/src/mainboard/google/veyron_brain/romstage.c
@@ -78,6 +78,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();
 

src/mainboard/google/veyron_danger/romstage.c

diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c
index d0e194b..e320898 100644
--- a/src/mainboard/google/veyron_danger/romstage.c
+++ b/src/mainboard/google/veyron_danger/romstage.c
@@ -79,6 +79,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();
 

src/mainboard/google/veyron_emile/romstage.c

diff --git a/src/mainboard/google/veyron_emile/romstage.c b/src/mainboard/google/veyron_emile/romstage.c
index bddc56b..dc4fe6c 100644
--- a/src/mainboard/google/veyron_emile/romstage.c
+++ b/src/mainboard/google/veyron_emile/romstage.c
@@ -78,6 +78,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();
 

src/mainboard/google/veyron_mickey/romstage.c

diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index 8b5b660..1c139f1 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -78,6 +78,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();
 

src/mainboard/google/veyron_rialto/romstage.c

diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index 9dfcfb2..62a03f5 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -85,6 +85,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();
 

src/mainboard/google/veyron_romy/romstage.c

diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c
index 8b5b660..1c139f1 100644
--- a/src/mainboard/google/veyron_romy/romstage.c
+++ b/src/mainboard/google/veyron_romy/romstage.c
@@ -78,6 +78,7 @@
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	console_init();
+	exception_init();
 	configure_l2ctlr();
 	tsadc_init();