diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 6aa33ca..63dff6a 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -23,20 +23,17 @@
  */
 
 #include <arch/acpi.h>
-#include <device/mmio.h>
-#include <device/pci_ops.h>
 #include <console/console.h>
-#include <device/pci_ids.h>
+#include <device/device.h>
+#include <device/mmio.h>
+#include <device/pci.h>
 #include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include <delay.h>
 #include <elog.h>
 
-#ifndef __SMM__
-#include <device/device.h>
-#include <device/pci.h>
-#endif
-
 #include "me.h"
 #include "pch.h"
 
@@ -44,9 +41,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
 
-#ifndef __SMM__
 /* Path that the BIOS should take based on ME state */
-static const char *me_bios_path_values[] = {
+static const char *me_bios_path_values[] __unused = {
 	[ME_NORMAL_BIOS_PATH]		= "Normal",
 	[ME_S3WAKE_BIOS_PATH]		= "S3 Wake",
 	[ME_ERROR_BIOS_PATH]		= "Error",
@@ -54,7 +50,6 @@
 	[ME_DISABLE_BIOS_PATH]		= "Disable",
 	[ME_FIRMWARE_UPDATE_BIOS_PATH]	= "Firmware Update",
 };
-#endif
 
 /* MMIO base address for MEI interface */
 static u32 *mei_base_address;
@@ -111,7 +106,7 @@
 	mei_dump(ptr, dword, offset, "WRITE");
 }
 
-#ifndef __SMM__
+#ifndef __SIMPLE_DEVICE__
 static inline void pci_read_dword_ptr(struct device *dev,void *ptr,
 				      int offset)
 {
@@ -131,7 +126,6 @@
 	mei_write_dword_ptr(csr, MEI_H_CSR);
 }
 
-#ifdef __SMM__
 static inline void read_me_csr(struct mei_csr *csr)
 {
 	mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
@@ -348,7 +342,7 @@
 }
 
 /* Send END OF POST message to the ME */
-static int mkhi_end_of_post(void)
+static int __unused mkhi_end_of_post(void)
 {
 	struct mkhi_header mkhi = {
 		.group_id	= MKHI_GROUP_ID_GEN,
@@ -371,6 +365,8 @@
 	return 0;
 }
 
+#ifdef __SIMPLE_DEVICE__
+
 static void intel_me7_finalize_smm(void)
 {
 	struct me_hfs hfs;
@@ -420,7 +416,7 @@
 		printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did);
 	}
 }
-#else /* !__SMM__ */
+#else /* !__SIMPLE_DEVICE__ */
 
 /* Determine the path that we should take based on ME status */
 static me_bios_path intel_me_path(struct device *dev)
@@ -629,4 +625,4 @@
 	.devices	= pci_device_ids
 };
 
-#endif /* !__SMM__ */
+#endif /* !__SIMPLE_DEVICE__ */