1. vgabios removed, will go to extra repository
2. Rename sisnb.c to sis761.c
3. Delete many mis-definition for sis device in
src/include/device/pci_ids.h
4. Trim trailing spaces for all files
Signed-off-by: Morgan Tsai <my_tsai@sis.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/sis/sis966/sis966_early_setup_car.c b/src/southbridge/sis/sis966/sis966_early_setup_car.c
index 370951a..951cfe2 100644
--- a/src/southbridge/sis/sis966/sis966_early_setup_car.c
+++ b/src/southbridge/sis/sis966/sis966_early_setup_car.c
@@ -21,125 +21,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-static int set_ht_link_sis966(uint8_t ht_c_num)
-{
- unsigned vendorid = 0x10de;
- unsigned val = 0x01610109;
- /* Nvidia sis966 hardcode, hw can not set it automatically */
- return set_ht_link_buffer_counts_chain(ht_c_num, vendorid, val);
-}
-
-static void setup_ss_table(unsigned index, unsigned where, unsigned control, const unsigned int *register_values, int max)
-{
- int i;
-
- unsigned val;
-
- val = inl(control);
- val &= 0xfffffffe;
- outl(val, control);
-
- outl(0, index); //index
- for(i = 0; i < max; i++) {
- unsigned long reg;
- reg = register_values[i];
- outl(reg, where);
- }
-
- val = inl(control);
- val |= 1;
- outl(val, control);
-
-}
-
-/* SIZE 0x100 */
-#define ANACTRL_IO_BASE 0x2800
-#define ANACTRL_REG_POS 0x68
-
-/* SIZE 0x100 */
-#define SYSCTRL_IO_BASE 0x2400
-#define SYSCTRL_REG_POS 0x64
-
-/* SIZE 0x100 */
-#define ACPICTRL_IO_BASE 0x2000
-#define ACPICTRL_REG_POS 0x60
-
-/*
- 16 1 1 1 1 8 :0
- 16 0 4 0 0 8 :1
- 16 0 4 2 2 4 :2
- 4 4 4 4 4 8 :3
- 8 8 4 0 0 8 :4
- 8 0 4 4 4 8 :5
-*/
-
-#ifndef SIS966_PCI_E_X_0
- #define SIS966_PCI_E_X_0 4
-#endif
-#ifndef SIS966_PCI_E_X_1
- #define SIS966_PCI_E_X_1 4
-#endif
-#ifndef SIS966_PCI_E_X_2
- #define SIS966_PCI_E_X_2 4
-#endif
-#ifndef SIS966_PCI_E_X_3
- #define SIS966_PCI_E_X_3 4
-#endif
-
-#ifndef SIS966_USE_NIC
- #define SIS966_USE_NIC 0
-#endif
-
-#ifndef SIS966_USE_AZA
- #define SIS966_USE_AZA 0
-#endif
-
-#define SIS966_CHIP_REV 3
-
-static void sis966_early_set_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base)
-{
-
- static const unsigned int ctrl_devport_conf[] = {
- PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), ANACTRL_IO_BASE,
- PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), SYSCTRL_IO_BASE,
- PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), ACPICTRL_IO_BASE,
- };
-
- int j;
- for(j = 0; j < sis966_num; j++ ) {
- setup_resource_map_offset(ctrl_devport_conf,
- sizeof(ctrl_devport_conf)/sizeof(ctrl_devport_conf[0]),
- PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
- }
-}
-
-static void sis966_early_clear_port(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base)
-{
-
- static const unsigned int ctrl_devport_conf_clear[] = {
- PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0,
- PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0,
- PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0,
- };
-
- int j;
- for(j = 0; j < sis966_num; j++ ) {
- setup_resource_map_offset(ctrl_devport_conf_clear,
- sizeof(ctrl_devport_conf_clear)/sizeof(ctrl_devport_conf_clear[0]),
- PCI_DEV(busn[j], devn[j], 0) , io_base[j]);
- }
-
-
-}
-static void delayx(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x8000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-
static void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x)
{
uint32_t tgio_ctrl;
@@ -170,260 +51,13 @@
outl(tgio_ctrl, anactrl_io_base + 0xcc);
// wait 100us
- delayx(1);
+ udelay(100);
dword = pci_read_config32(dev, 0xe4);
dword &= ~(0x3f0); // enable
pci_write_config32(dev, 0xe4, dword);
// need to wait 100ms
- delayx(1000);
+ mdelay(100);
}
-static void sis966_early_setup(unsigned sis966_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
-{
-
- static const unsigned int ctrl_conf_1[] = {
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x10, 0x0007ffff, 0xff78000,
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xa4, 0xffedffff, 0x0012000,
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xac, 0xfffffdff, 0x0000200,
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0xb4, 0xfffffffd, 0x0000002,
-
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x24, 0xc0f0f08f, 0x26020230,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x34, 0x00000000, 0x22222222,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x08, 0x7FFFFFFF, 0x00000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x2C, 0x7FFFFFFF, 0x80000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000200,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0xCC, 0xFFFFF9FF, 0x00000400,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x30, 0x8FFFFFFF, 0x40000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x74, 0xFFFF0FF5, 0x0000F000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x78, 0xFF00FF00, 0x00100010,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x7C, 0xFF0FF0FF, 0x00500500,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, 0xFFFFFFE7, 0x00000000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFCFFFFF, 0x00300000,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x90, 0xFFFF00FF, 0x0000FF00,
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x9C, 0xFF00FFFF, 0x00070000,
-
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x48), 0xFFFFDCED, 0x00002002,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x78), 0xFFFFFF8E, 0x00000011,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x80), 0xFFFF0000, 0x00009923,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x88), 0xFFFFFFFE, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x8C), 0xFFFF0000, 0x0000007F,
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xDC), 0xFFFEFFFF, 0x00010000,
-
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFFFF7B, 0x00000084,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
-
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xC4), 0xFFFFFFFE, 0x00000001,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF0), 0x7FFFFFFD, 0x00000002,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
-
- RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 8, 0, 0x68), 0xFFFFFF00, 0x000000FF,
- RES_PCI_IO, PCI_ADDR(0, 8, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
-
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0x68), 0xFFFFFF00, 0x000000FF,
- RES_PCI_IO, PCI_ADDR(0, 9, 0, 0xF8), 0xFFFFFFBF, 0x00000040,//Enable bridge mode
- };
-
- static const unsigned int ctrl_conf_1_1[] = {
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x50), 0xFFFFFFFC, 0x00000003,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x64), 0xFFFFFFFE, 0x00000001,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x70), 0xFFF0FFFF, 0x00040000,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xAC), 0xFFFFF0FF, 0x00000100,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0x7C), 0xFFFFFFEF, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xC8), 0xFF00FF00, 0x000A000A,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xD0), 0xF0FFFFFF, 0x03000000,
- RES_PCI_IO, PCI_ADDR(0, 5, 0, 0xE0), 0xF0FFFFFF, 0x03000000,
- };
-
-
- static const unsigned int ctrl_conf_sis966_only[] = {
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE0), 0xFFFFFEFF, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), 0xFFFFFFFB, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE8), 0xFFA9C8FF, 0x00003000,
-
-// RES_PCI_IO, PCI_ADDR(0, 4, 0, 0x40), 0x00000000, 0xCB8410DE,
-// RES_PCI_IO, PCI_ADDR(0, 4, 0, 0xF8), 0xFFFFFFCF, 0x00000010,
-
- RES_PCI_IO, PCI_ADDR(0, 2, 0, 0x40), 0x00000000, 0xCB8410DE,
-
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x40), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x64), 0xF87FFFFF, 0x05000000,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x78), 0xFFC07FFF, 0x00360000,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x68), 0xFE00D03F, 0x013F2C00,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x70), 0xFFF7FFFF, 0x00080000,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0x7C), 0xFFFFF00F, 0x00000570,
- RES_PCI_IO, PCI_ADDR(0, 2, 1, 0xF8), 0xFFFFFFCF, 0x00000010,
-
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x04), 0xFFFFFEFB, 0x00000104,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x3C), 0xF5FFFFFF, 0x0A000000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x40), 0x00C8FFFF, 0x07330000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x48), 0xFFFFFFF8, 0x00000005,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x4C), 0xFE02FFFF, 0x004C0000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0x74), 0xFFFFFFC0, 0x00000000,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC0), 0x00000000, 0xCB8410DE,
- RES_PCI_IO, PCI_ADDR(0, 6, 0, 0xC4), 0xFFFFFFF8, 0x00000007,
-
-#if SIS966_USE_AZA == 1
- RES_PCI_IO, PCI_ADDR(0, 6, 1, 0x40), 0x00000000, 0xCB8410DE,
-
-// RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xE4), ~(1<<14), 1<<14,
-#endif
-// play a while with GPIO in SIS966
-#ifdef SIS966_MB_SETUP
- SIS966_MB_SETUP
-#endif
-
-#if SIS966_USE_AZA == 1
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 21, ~(3<<2), (2<<2),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 22, ~(3<<2), (2<<2),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 46, ~(3<<2), (2<<2),
-#endif
-
-
- };
-
- static const unsigned int ctrl_conf_master_only[] = {
-
- RES_PORT_IO_32, ACPICTRL_IO_BASE + 0x80, 0xEFFFFFF, 0x01000000,
-
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78), 0xC0FFFFFF, 0x19000000,
-
- //Master SIS966 ????YHLU
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 0, ~(3<<2), (0<<2),
-
- };
-
- static const unsigned int ctrl_conf_2[] = {
- /* I didn't put pcie related stuff here */
-
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x74), 0xFFFFF00F, 0x000009D0,
- RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x74), 0xFFFF7FFF, 0x00008000,
-
- RES_PORT_IO_32, SYSCTRL_IO_BASE + 0x48, 0xFFFEFFFF, 0x00010000,
-
- RES_PORT_IO_32, ANACTRL_IO_BASE + 0x60, 0xFFFFFF00, 0x00000012,
-
-
-#if SIS966_USE_NIC == 1
- RES_PCI_IO, PCI_ADDR(0, 1, 1, 0xe4), ~((1<<22)|(1<<20)), (1<<22)|(1<<20),
-
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 4, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
-#endif
-
- };
-
-
- int j, i;
-
- for(j=0; j<sis966_num; j++) {
- sis966_early_pcie_setup(busn[j], devn[j], io_base[j] + ANACTRL_IO_BASE, pci_e_x[j]);
-
- setup_resource_map_x_offset(ctrl_conf_1, sizeof(ctrl_conf_1)/sizeof(ctrl_conf_1[0]),
- PCI_DEV(busn[j], devn[j], 0), io_base[j]);
- for(i=0; i<3; i++) { // three SATA
- setup_resource_map_x_offset(ctrl_conf_1_1, sizeof(ctrl_conf_1_1)/sizeof(ctrl_conf_1_1[0]),
- PCI_DEV(busn[j], devn[j], i), io_base[j]);
- }
- if(busn[j] == 0) {
- setup_resource_map_x_offset(ctrl_conf_sis966_only, sizeof(ctrl_conf_sis966_only)/sizeof(ctrl_conf_sis966_only[0]),
- PCI_DEV(busn[j], devn[j], 0), io_base[j]);
- }
-
- if( (busn[j] == 0) && (sis966_num>1) ) {
- setup_resource_map_x_offset(ctrl_conf_master_only, sizeof(ctrl_conf_master_only)/sizeof(ctrl_conf_master_only[0]),
- PCI_DEV(busn[j], devn[j], 0), io_base[j]);
- }
-
- setup_resource_map_x_offset(ctrl_conf_2, sizeof(ctrl_conf_2)/sizeof(ctrl_conf_2[0]),
- PCI_DEV(busn[j], devn[j], 0), io_base[j]);
-
- }
-
-#if 0
- for(j=0; j< sis966_num; j++) {
- // PCI-E (XSPLL) SS table 0x40, x044, 0x48
- // SATA (SPPLL) SS table 0xb0, 0xb4, 0xb8
- // CPU (PPLL) SS table 0xc0, 0xc4, 0xc8
- setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0x40, io_base[j] + ANACTRL_IO_BASE+0x44,
- io_base[j] + ANACTRL_IO_BASE+0x48, pcie_ss_tbl, 64);
- setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xb0, io_base[j] + ANACTRL_IO_BASE+0xb4,
- io_base[j] + ANACTRL_IO_BASE+0xb8, sata_ss_tbl, 64);
- setup_ss_table(io_base[j] + ANACTRL_IO_BASE+0xc0, io_base[j] + ANACTRL_IO_BASE+0xc4,
- io_base[j] + ANACTRL_IO_BASE+0xc8, cpu_ss_tbl, 64);
- }
-#endif
-
-}
-
-#ifndef HT_CHAIN_NUM_MAX
-
-#define HT_CHAIN_NUM_MAX 4
-#define HT_CHAIN_BUSN_D 0x40
-#define HT_CHAIN_IOBASE_D 0x4000
-
-#endif
-
-static int sis966_early_setup_x(void)
-{
- /*find out how many sis966 we have */
- unsigned busn[HT_CHAIN_NUM_MAX];
- unsigned devn[HT_CHAIN_NUM_MAX];
- unsigned io_base[HT_CHAIN_NUM_MAX];
- /*
- FIXME: May have problem if there is different SIS966 HTX card with different PCI_E lane allocation
- Need to use same trick about pci1234 to verify node/link connection
- */
- unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {SIS966_PCI_E_X_0, SIS966_PCI_E_X_1, SIS966_PCI_E_X_2, SIS966_PCI_E_X_3 };
- int sis966_num = 0;
- unsigned busnx;
- unsigned devnx;
- int ht_c_index,j;
-
- /* FIXME: multi pci segment handling */
-
- /* Any system that only have IO55 without SIS966? */
- for(ht_c_index = 0; ht_c_index<HT_CHAIN_NUM_MAX; ht_c_index++) {
- busnx = ht_c_index * HT_CHAIN_BUSN_D;
- for(devnx=0;devnx<0x20;devnx++) {
- uint32_t id;
- device_t dev;
- dev = PCI_DEV(busnx, devnx, 0);
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if(id == 0x036910de) {
- busn[sis966_num] = busnx;
- devn[sis966_num] = devnx;
- io_base[sis966_num] = ht_c_index * HT_CHAIN_IOBASE_D; // we may have ht chain other than SIS966
- sis966_num++;
- if(sis966_num == SIS966_NUM) goto out;
- break; // only one SIS966 on one chain
- }
- }
- }
-
-out:
- print_debug("sis966_num:"); print_debug_hex8(sis966_num); print_debug("\r\n");
-
- //sis966_early_set_port(sis966_num, busn, devn, io_base);
- //sis966_early_setup(sis966_num, busn, devn, io_base, pci_e_x);
-
- //sis966_early_clear_port(sis966_num, busn, devn, io_base);
-
-// set_ht_link_sis966(HT_CHAIN_NUM_MAX);
-
- return 0;
-
-}
-
-
-