arch/riscv: Use 'enum cb_err'
Change-Id: I5a589a43b1e92cca6b531ca161174eefb5592569
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c
index a17b7dd..9f144b8 100644
--- a/src/arch/riscv/misaligned.c
+++ b/src/arch/riscv/misaligned.c
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <stdint.h>
#include <vm.h>
#include <arch/exception.h>
#include <commonlib/helpers.h>
+#include <types.h>
/* these functions are defined in src/arch/riscv/fp_asm.S */
#if defined(__riscv_flen)
@@ -131,18 +131,18 @@
return NULL;
}
-static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
+static enum cb_err fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
{
uint16_t ins = mprv_read_mxr_u16((uint16_t *)vaddr);
if (EXTRACT_FIELD(ins, 0x3) != 3) {
*insn = ins;
*size = 2;
- return 0;
+ return CB_SUCCESS;
}
- return -1;
+ return CB_ERR;
}
-static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
+static enum cb_err fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
{
uint32_t l = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 0);
uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 1);
@@ -151,9 +151,9 @@
(EXTRACT_FIELD(ins, 0x1c) != 0x7)) {
*insn = ins;
*size = 4;
- return 0;
+ return CB_SUCCESS;
}
- return -1;
+ return CB_ERR;
}
void handle_misaligned(trapframe *tf)