diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 2d2023b..c08f0da 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_def.h>
+#include "iobp.h"
 #include "pch.h"
 
 #ifdef __SIMPLE_DEVICE__
@@ -183,110 +184,6 @@
 	}
 }
 
-#define IOBP_RETRY 1000
-static inline int iobp_poll(void)
-{
-	unsigned int try;
-
-	for (try = IOBP_RETRY; try > 0; try--) {
-		u16 status = RCBA16(IOBPS);
-		if ((status & IOBPS_READY) == 0)
-			return 1;
-		udelay(10);
-	}
-
-	printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n");
-	return 0;
-}
-
-u32 pch_iobp_read(u32 address)
-{
-	u16 status;
-
-	if (!iobp_poll())
-		return 0;
-
-	/* Set the address */
-	RCBA32(IOBPIRI) = address;
-
-	/* READ OPCODE */
-	status = RCBA16(IOBPS);
-	status &= ~IOBPS_MASK;
-	status |= IOBPS_READ;
-	RCBA16(IOBPS) = status;
-
-	/* Undocumented magic */
-	RCBA16(IOBPU) = IOBPU_MAGIC;
-
-	/* Set ready bit */
-	status = RCBA16(IOBPS);
-	status |= IOBPS_READY;
-	RCBA16(IOBPS) = status;
-
-	if (!iobp_poll())
-		return 0;
-
-	/* Check for successful transaction */
-	status = RCBA16(IOBPS);
-	if (status & IOBPS_TX_MASK) {
-		printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address);
-		return 0;
-	}
-
-	/* Read IOBP data */
-	return RCBA32(IOBPD);
-}
-
-void pch_iobp_write(u32 address, u32 data)
-{
-	u16 status;
-
-	if (!iobp_poll())
-		return;
-
-	/* Set the address */
-	RCBA32(IOBPIRI) = address;
-
-	/* WRITE OPCODE */
-	status = RCBA16(IOBPS);
-	status &= ~IOBPS_MASK;
-	status |= IOBPS_WRITE;
-	RCBA16(IOBPS) = status;
-
-	RCBA32(IOBPD) = data;
-
-	/* Undocumented magic */
-	RCBA16(IOBPU) = IOBPU_MAGIC;
-
-	/* Set ready bit */
-	status = RCBA16(IOBPS);
-	status |= IOBPS_READY;
-	RCBA16(IOBPS) = status;
-
-	if (!iobp_poll())
-		return;
-
-	/* Check for successful transaction */
-	status = RCBA16(IOBPS);
-	if (status & IOBPS_TX_MASK) {
-		printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address);
-		return;
-	}
-
-	printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data);
-}
-
-void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
-{
-	u32 data = pch_iobp_read(address);
-
-	/* Update the data */
-	data &= andvalue;
-	data |= orvalue;
-
-	pch_iobp_write(address, data);
-}
-
 void pch_enable(struct device *dev)
 {
 	/* PCH PCIe Root Ports are handled in PCIe driver. */