commit 205e7f676d3e65bf99ca27107cef34ee0a8a4049
author Tim Crawford <tcrawford@system76.com> Tue Jul 12 13:16:56 2022 -0600
committer Martin L Roth <gaumless@tutanota.com> Sat Jul 16 22:55:54 2022 +0000
tree 13cc84cc7c5adb1afdfbe2ee3f1c0498297733f4
parent 4060df41b2fa706cf9d674c84fa6443426d0b4d3

mb/system76/oryp5: Configure dGPU GPIOs in bootblock

Configure the dGPU power and reset pins in bootblock instead of
ramstage. This fixes a conflict with our downstream driver, which
configures these pins to enable dGPU power in romstage. Behavior remains
unchanged without the driver as the dGPU is left powered off.

Change-Id: Ica5ad5adc20fc2629d913b76a5a781fbd59a569d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

src/mainboard/system76/oryp5/gpio.c

diff --git a/src/mainboard/system76/oryp5/gpio.c b/src/mainboard/system76/oryp5/gpio.c
index c97d1aa..02cb3c0 100644
--- a/src/mainboard/system76/oryp5/gpio.c
+++ b/src/mainboard/system76/oryp5/gpio.c
@@ -164,8 +164,8 @@
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
 	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
 	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
-	PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
-	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
+	// GPP_F22 (DGPU_RST#_PCH) configured in bootblock
+	// GPP_F23 (DGPU_PWR_EN) configured in bootblock
 
 	/* ------- GPIO Group GPP_G ------- */
 	PAD_NC(GPP_G0, NONE),

src/mainboard/system76/oryp5/gpio_early.c

diff --git a/src/mainboard/system76/oryp5/gpio_early.c b/src/mainboard/system76/oryp5/gpio_early.c
index 80f37c6..5423fd1 100644
--- a/src/mainboard/system76/oryp5/gpio_early.c
+++ b/src/mainboard/system76/oryp5/gpio_early.c
@@ -6,6 +6,8 @@
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F23, 0, DEEP), // DGPU_PWR_EN
 };
 
 void mainboard_configure_early_gpios(void)