diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 971dda3..b570b01 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -110,4 +110,13 @@
 config RISCV_WORKING_HARTID
 	int
 
+# Newer SoC have the menvconfig register.
+# Very few SOC do not have this.
+# Older SoC, such as the SiFive FU[57]40, that
+# do not have this register, should set this
+# to n.
+config RISCV_SOC_HAS_MENVCFG
+	bool
+	default y
+
 endif # if ARCH_RISCV
diff --git a/src/arch/riscv/include/arch/encoding.h b/src/arch/riscv/include/arch/encoding.h
index 4f01e5c..6ab38bb 100644
--- a/src/arch/riscv/include/arch/encoding.h
+++ b/src/arch/riscv/include/arch/encoding.h
@@ -800,6 +800,8 @@
 #define CSR_MIE 0x304
 #define CSR_MTVEC 0x305
 #define CSR_MCOUNTEREN 0x306
+#define CSR_MENVCFG 0x30a
+#define CSR_MENVCFGH 0x31a
 #define CSR_MSCRATCH 0x340
 #define CSR_MEPC 0x341
 #define CSR_MCAUSE 0x342
@@ -1292,6 +1294,8 @@
 DECLARE_CSR(mie, CSR_MIE)
 DECLARE_CSR(mtvec, CSR_MTVEC)
 DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(menvcfg, CSR_MENVCFG)
+DECLARE_CSR(menvcfgh, CSR_MENVCFGH)
 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index 97931fd..fb15762 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -48,4 +48,9 @@
 config OPENSBI_TEXT_START
 	hex
 	default 0x80000000
+
+config RISCV_SOC_HAS_MENVCFG
+	bool
+	default n
+
 endif
diff --git a/src/soc/sifive/fu740/Kconfig b/src/soc/sifive/fu740/Kconfig
index 0c62e1e..f6c2d59 100644
--- a/src/soc/sifive/fu740/Kconfig
+++ b/src/soc/sifive/fu740/Kconfig
@@ -60,4 +60,8 @@
 	  Choose the first U74 core as boot hart since
 	  hart 0 is the S7 which does not support Supervisor mode
 
+config RISCV_SOC_HAS_MENVCFG
+	bool
+	default n
+
 endif