superio/nuvoton/nct6779d: Open some LDN config registers
The porting of Asus P8Z77-M mainboard required changing certain Super
I/O configuration registers that were ignored in devicetree.cb because
they aren't listed as resources. Add the declaration so they can be
changed.
This change is nowhere near enough as the current structure is
insufficient to allow changing configuration registers in the 0xE?
range, which this board also needs.
TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when
inspected using superiotool -d.
Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c
index 843857c..ef50aa6 100644
--- a/src/superio/nuvoton/nct6779d/superio.c
+++ b/src/superio/nuvoton/nct6779d/superio.c
@@ -37,8 +37,8 @@
{ NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
0x0fff, 0x0fff, },
{ NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
- { NULL, NCT6779D_ACPI},
- { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+ { NULL, NCT6779D_ACPI, PNP_MSC2,},
+ { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
0x0ffe, 0x0ffe, },
{ NULL, NCT6779D_WDT1},
{ NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, },
@@ -51,8 +51,8 @@
{ NULL, NCT6779D_GPIO2},
{ NULL, NCT6779D_GPIO3},
{ NULL, NCT6779D_GPIO4},
- { NULL, NCT6779D_GPIO5},
- { NULL, NCT6779D_GPIO6},
+ { NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5},
+ { NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5},
{ NULL, NCT6779D_GPIO7},
{ NULL, NCT6779D_GPIO8},
};