commit 1ef547eec7262f96770f1fe4d1c6ff44b624dbe2
author Elyes Haouas <ehaouas@noos.fr> Fri Nov 18 15:05:39 2022 +0100
committer Felix Held <felix-coreboot@felixheld.de> Tue Nov 22 13:40:56 2022 +0000
tree 208ee987a82a1a5db011fccab7e6a9ed9ef8cdb4
parent 385939f7cfeeb732c4a54f6069940c2a7de53579

src/drivers: Remove unnecessary space after casts

Change-Id: I16689da893b5a0c3254364759d435281cb3e1caf
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69803
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/fsp2_0/silicon_init.c

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 87f77a2..678892a 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -96,7 +96,7 @@
 	struct fsp_multi_phase_params multi_phase_params;
 	struct fsp_multi_phase_get_number_of_phases_params multi_phase_get_number;
 
-	supd = (FSPS_UPD *) (uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
+	supd = (FSPS_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base);
 
 	fsp_verify_upd_header_signature(supd->FspUpdHeader.Signature, FSPS_UPD_SIGNATURE);
 
@@ -127,7 +127,7 @@
 		soc_load_logo(upd);
 
 	/* Call SiliconInit */
-	silicon_init = (void *) (uintptr_t)(hdr->image_base +
+	silicon_init = (void *)(uintptr_t)(hdr->image_base +
 				 hdr->fsp_silicon_init_entry_offset);
 	fsp_debug_before_silicon_init(silicon_init, supd, upd);
 
@@ -165,7 +165,7 @@
 		return;
 
 	/* Call MultiPhaseSiInit */
-	multi_phase_si_init = (void *) (uintptr_t)(hdr->image_base +
+	multi_phase_si_init = (void *)(uintptr_t)(hdr->image_base +
 			 hdr->fsp_multi_phase_si_init_entry_offset);
 
 	/* Implementing multi_phase_si_init() is optional as per FSP 2.2 spec */