nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree
Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb
index 5f945c1..9e5c136 100644
--- a/src/mainboard/intel/dg41wv/devicetree.cb
+++ b/src/mainboard/intel/dg41wv/devicetree.cb
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
chip northbridge/intel/x4x # Northbridge
- device cpu_cluster 0 on # APIC cluster
+ device cpu_cluster 0 on
+ ops x4x_cpu_bus_ops # APIC cluster
chip cpu/intel/socket_LGA775
device lapic 0 on end
end
@@ -9,7 +10,8 @@
device lapic 0xACAC off end
end
end
- device domain 0 on # PCI domain
+ device domain 0 on
+ ops x4x_pci_domain_ops # PCI domain
subsystemid 0x1458 0x5000 inherit
device pci 0.0 on # Host Bridge
subsystemid 0x8086 0x5756