commit 1e7582650e6523f097d633c3bf9a4bcde1b27750
author Nick Vaccaro <nvaccaro@google.com> Fri Jun 11 18:05:48 2021 -0700
committer Nick Vaccaro <nvaccaro@google.com> Mon Jun 14 17:46:51 2021 +0000
tree 5eb4cf516baf6a90bdf110e534e3520402a0a379
parent ae10d8119ee235b8421227ba0fcecd6e8ac189d6

mb/google/volteer/var/drobit: change GPP_B2 to PLTRST

Change GPP_B2 (EN_PP3300_SSD) to PLTRST to avoid S3 resume hang.
Add GPP_B2 to the early_gpio_table.

BUG=b:174776411
BRANCH=none
TEST=none

Change-Id: I49f7b1b69c3c3ab5593c7230d8f631a3b54c9c9d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/google/volteer/variants/drobit/gpio.c

diff --git a/src/mainboard/google/volteer/variants/drobit/gpio.c b/src/mainboard/google/volteer/variants/drobit/gpio.c
index 7e857ea..f3d8947 100644
--- a/src/mainboard/google/volteer/variants/drobit/gpio.c
+++ b/src/mainboard/google/volteer/variants/drobit/gpio.c
@@ -25,7 +25,7 @@
 	PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
 
 	/* B2  : VRALERT# ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_B2, 1, DEEP),
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
 	/* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
 	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
 	/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
@@ -143,6 +143,8 @@
 	/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
 	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
 
+	/* B2  : VRALERT# ==> EN_PP3300_SSD */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
 	/* B11 : PMCALERT# ==> PCH_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
 	/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */