#
# This file is part of the coreboot project.
#
# Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
chip northbridge/amd/pi/00670F00/root_complex
	device cpu_cluster 0 on
		chip cpu/amd/pi/00670F00
			device lapic 10 on end
		end
	end

	device domain 0 on
		subsystemid 0x1022 0x1410 inherit
		chip northbridge/amd/pi/00670F00 # CPU side of HT root complex

			chip northbridge/amd/pi/00670F00 # PCI side of HT root complex
				device pci 0.0 on  end # Root Complex
				device pci 1.0 on  end # Internal Graphics P2P bridge 0x98e4
				device pci 1.1 on  end # Internal Multimedia
				device pci 2.0 on  end # PCIe Host Bridge
				device pci 2.1 on  end # x4 PCIe slot
				device pci 2.2 on  end # M.2 slot
				device pci 2.3 on  end # M.2 slot
				device pci 2.4 on  end # x1 PCIe slot
				device pci 2.5 on  end # Cardreader
			end	#chip northbridge/amd/pi/00670F00

			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
				device pci 9.0 on  end # PCIe Host Bridge
				device pci 9.2 on  end # HDA
				device pci 10.0 on  end # xHCI
				device pci 11.0 on  end # SATA
				device pci 12.0 on  end # EHCI
				device pci 14.0 on      # SM
					chip drivers/generic/generic # dimm 0-0-0
						device i2c 51 on end
					end
				end # SM
				device pci 14.3 on  end # LPC	0x790e
				device pci 14.7 on  end # SD
			end	#chip southbridge/amd/pi/hudson

			device pci 18.0 on  end
			device pci 18.1 on  end
			device pci 18.2 on  end
			device pci 18.3 on  end
			device pci 18.4 on  end
			device pci 18.5 on  end
			register "spdAddrLookup" = "
			{
				{ {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
			}"

		end #chip northbridge/amd/pi/00670F00 # CPU side of HT root complex
	end #domain
end #northbridge/amd/pi/00670F00/root_complex