soc/intel/quark: Pass S3 wake status to fsp_silicon_init
Fix build error with FSP 1.1. Pass the S3 wake status to
fsp_silicon_init.
TEST=Build and run on Galileo Gen2
Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18805
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/quark/fsp1_1.c b/src/soc/intel/quark/fsp1_1.c
index ee10e38..1178031 100644
--- a/src/soc/intel/quark/fsp1_1.c
+++ b/src/soc/intel/quark/fsp1_1.c
@@ -17,12 +17,12 @@
#include <fsp/util.h>
#include <soc/ramstage.h>
-void fsp_silicon_init(void)
+void fsp_silicon_init(bool s3wake)
{
if (IS_ENABLED(CONFIG_RELOCATE_FSP_INTO_DRAM))
intel_silicon_init();
else
- fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), 0);
+ fsp_run_silicon_init(find_fsp(CONFIG_FSP_ESRAM_LOC), s3wake);
}
void soc_silicon_init_params(SILICON_INIT_UPD *upd)
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
index 0ff2128..9187487 100644
--- a/src/soc/intel/quark/include/soc/ramstage.h
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -26,7 +26,7 @@
void mainboard_gpio_i2c_init(device_t dev);
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
-void fsp_silicon_init(void);
+void fsp_silicon_init(bool s3wake);
#endif
asmlinkage void chipset_teardown_car(void);