soc/intel/common: Introduce SOC_INTEL_COMPLIANCE_TEST_MODE
This config can be used to make coreboot configure the hardware to
meet compliance tests requirements. SoCs which support compliance
testing features should set the
SOC_INTEL_SUPPORTS_COMPLIANCE_TEST_MODE flag.
BUG=b:235863379
TEST=Successful compilation
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Iec760ae89e2b892ef45e6750e823ab5a8609d0fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/Kconfig.common b/src/soc/intel/common/Kconfig.common
index 4b620a6..29d1c7c 100644
--- a/src/soc/intel/common/Kconfig.common
+++ b/src/soc/intel/common/Kconfig.common
@@ -113,6 +113,24 @@
Set this option to enable default debug interface of SoC such as DBC
or DCI.
+config HAVE_INTEL_COMPLIANCE_TEST_MODE
+ def_bool n
+
+config SOC_INTEL_COMPLIANCE_TEST_MODE
+ bool "Enable SoC hardware compliance test mode"
+ depends on HAVE_INTEL_COMPLIANCE_TEST_MODE
+ default n
+ help
+ Set this option to configure hardware components in a way
+ that supports compliance testing activities for various
+ components such PCIe or USB. For example, PCI express
+ implementation must comply with the hardware PCIe
+ specification requirements: Electrical, Configuration, Link
+ Protocol and Transaction Protocol. The hardware must be
+ configured in a particular state to run the compliance
+ tests: some feature related to power management needs to be
+ turned off, hot plug should be enabled...
+
config SMM_MODULE_STACK_SIZE
hex
default 0x800