| commit | 1d3e6eba02b074cf02615037694563db8854d3f1 | [log] [tgz] |
|---|---|---|
| author | Tim Crawford <tcrawford@system76.com> | Mon Jul 31 14:15:27 2023 -0600 |
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | Sat Aug 05 16:09:27 2023 +0000 |
| tree | 54fc4bc4e6d5e4d426a4facf2fe2ebf38f7719a0 | |
| parent | c9f99e5632f08f91cc23a96eef54f573078155bc [diff] |
mb/system76: Enable C10 reporting on systems using eSPI Report CPU C10 state over eSPI so that the EC can use Virtual Wires to detect if PECI can be used. Change-Id: I301361f35caee8ba1c3fd9227219603897add92b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/system76/adl/ramstage.c b/src/mainboard/system76/adl/ramstage.c index c767f2d..aa9a1b7 100644 --- a/src/mainboard/system76/adl/ramstage.c +++ b/src/mainboard/system76/adl/ramstage.c
@@ -17,6 +17,9 @@ params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 params->SataPortsSolidStateDrive[1] = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; } static void mainboard_init(void *chip_info)
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c index 9d98563..0d4ae48 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
@@ -18,4 +18,7 @@ // Remap PEG2 as PEG1 params->CpuPcieRpFunctionSwap = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; }
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c index 0f83461..93808a1 100644 --- a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c +++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
@@ -15,4 +15,7 @@ params->CpuPcieRpAdvancedErrorReporting[1] = 0; params->CpuPcieRpLtrEnable[1] = 1; params->CpuPcieRpPtmEnabled[1] = 0; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; }
diff --git a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c index 72ad3fc..bb50326 100644 --- a/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c +++ b/src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c
@@ -21,4 +21,7 @@ // Low latency legacy I/O params->PchLegacyIoLowLatency = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; }