soc/intel: Add Skylake SOC support
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index ae0f980..52029fc 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,13 +1,9 @@
-cpu_incs += $(src)/soc/intel/broadwell/romstage/cache_as_ram.inc
-
romstage-y += cpu.c
romstage-y += pch.c
romstage-y += power_state.c
-romstage-y += raminit.c
romstage-y += report_platform.c
romstage-y += romstage.c
romstage-y += smbus.c
romstage-y += spi.c
-romstage-y += stack.c
romstage-y += systemagent.c
-romstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart.c
+romstage-$(CONFIG_INTEL_PCH_UART_CONSOLE) += uart.c
diff --git a/src/soc/intel/skylake/romstage/cache_as_ram.inc b/src/soc/intel/skylake/romstage/cache_as_ram.inc
deleted file mode 100644
index a10ca4c..0000000
--- a/src/soc/intel/skylake/romstage/cache_as_ram.inc
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/post_code.h>
-#include <cbmem.h>
-
-/* The full cache-as-ram size includes the cache-as-ram portion from coreboot
- * and the space used by the reference code. These 2 values combined should
- * be a power of 2 because the MTRR setup assumes that. */
-#define CACHE_AS_RAM_SIZE \
- (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE)
-#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define CACHE_AS_RAM_LIMIT (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
-#define USBDEBUG_VAR_SIZE 36 /* sizeof(struct ehci_debug_info) */
-
-/* Cache 4GB - MRC_SIZE_KB for MRC */
-#define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
-#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
-#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
-
-#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS
-#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
-
-#define NoEvictMod_MSR 0x2e0
-
- /* Save the BIST result. */
- movl %eax, %ebp
-
-cache_as_ram:
- post_code(0x20)
-
- /* Send INIT IPI to all excluding ourself. */
- movl $0x000C4500, %eax
- movl $0xFEE00300, %esi
- movl %eax, (%esi)
-
- /* All CPUs need to be in Wait for SIPI state */
-wait_for_sipi:
- movl (%esi), %eax
- bt $12, %eax
- jc wait_for_sipi
-
- post_code(0x21)
- /* Zero out all fixed range and variable range MTRRs. */
- movl $mtrr_table, %esi
- movl $((mtrr_table_end - mtrr_table) / 2), %edi
- xorl %eax, %eax
- xorl %edx, %edx
-clear_mtrrs:
- movw (%esi), %bx
- movzx %bx, %ecx
- wrmsr
- add $2, %esi
- dec %edi
- jnz clear_mtrrs
-
- post_code(0x22)
- /* Configure the default memory type to uncacheable. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~0x00000cff), %eax
- wrmsr
-
- post_code(0x23)
- /* Set Cache-as-RAM base address. */
- movl $(MTRRphysBase_MSR(0)), %ecx
- movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
- xorl %edx, %edx
- wrmsr
-
- post_code(0x24)
- /* Set Cache-as-RAM mask. */
- movl $(MTRRphysMask_MSR(0)), %ecx
- movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-
- post_code(0x25)
-
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $MTRRdefTypeEn, %eax
- wrmsr
-
- /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- invd
- movl %eax, %cr0
-
- /* enable the 'no eviction' mode */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- orl $1, %eax
- andl $~2, %eax
- wrmsr
-
- /* Clear the cache memory region. This will also fill up the cache */
- movl $CACHE_AS_RAM_BASE, %esi
- movl %esi, %edi
- movl $(CACHE_AS_RAM_SIZE / 4), %ecx
- xorl %eax, %eax
- rep stosl
-
- /* enable the 'no eviction run' state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- orl $3, %eax
- wrmsr
-
- post_code(0x26)
- /* Enable Cache-as-RAM mode by disabling cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- /* Enable cache for our code in Flash because we do XIP here */
- movl $MTRRphysBase_MSR(1), %ecx
- xorl %edx, %edx
- /*
- * IMPORTANT: The following calculation _must_ be done at runtime. See
- * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
- */
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
- orl $MTRR_TYPE_WRPROT, %eax
- wrmsr
-
- movl $MTRRphysMask_MSR(1), %ecx
- movl $CPU_PHYSMASK_HI, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
- wrmsr
-
- post_code(0x27)
-#if CONFIG_CACHE_MRC_BIN
- /* Enable caching for ram init code to run faster */
- movl $MTRRphysBase_MSR(2), %ecx
- movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
- xorl %edx, %edx
- wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
- movl $CPU_PHYSMASK_HI, %edx
- wrmsr
-#endif
-
- post_code(0x28)
- /* Enable cache. */
- movl %cr0, %eax
- andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
- movl %eax, %cr0
-
- /* Setup the stack. */
- movl $(CACHE_AS_RAM_LIMIT), %eax
-#if CONFIG_USBDEBUG
- sub $(USBDEBUG_VAR_SIZE), %eax
-#endif
- movl %eax, %esp
-
- /* Restore the BIST result. */
- movl %ebp, %eax
-
- /* Build the call frame. */
- movl %esp, %ebp
- movd %mm1, %ebx
- pushl %ebx
- movd %mm0, %ebx
- pushl %ebx
- pushl %eax
-
-before_romstage:
- post_code(0x29)
- /* Call romstage.c main function. */
- call romstage_main
- /* Save return value from romstage_main. It contains the stack to use
- * after cache-as-ram is torn down. It also contains the information
- * for setting up MTRRs. */
- movl %eax, %ebx
-
- post_code(0x2f)
-
- /* Copy global variable space (for USBDEBUG) to memory */
-#if CONFIG_USBDEBUG
- cld
- movl $(CACHE_AS_RAM_LIMIT - USBDEBUG_VAR_SIZE), %esi
- movl $(CONFIG_RAMTOP - USBDEBUG_VAR_SIZE), %edi
- movl $USBDEBUG_VAR_SIZE, %ecx
- rep movsb
-#endif
-
- post_code(0x30)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x31)
-
- /* Disable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- andl $(~MTRRdefTypeEn), %eax
- wrmsr
-
- post_code(0x31)
-
- /* Disable the no eviction run state */
- movl $NoEvictMod_MSR, %ecx
- rdmsr
- andl $~2, %eax
- wrmsr
-
- invd
-
- /* Disable the no eviction mode */
- rdmsr
- andl $~1, %eax
- wrmsr
-
-#if CONFIG_CACHE_MRC_BIN
- /* Clear MTRR that was used to cache MRC */
- xorl %eax, %eax
- xorl %edx, %edx
- movl $MTRRphysBase_MSR(2), %ecx
- wrmsr
- movl $MTRRphysMask_MSR(2), %ecx
- wrmsr
-#endif
-
- post_code(0x33)
-
- /* Enable cache. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x36)
-
- /* Disable cache. */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- post_code(0x38)
-
- /* Setup stack as indicated by return value from ramstage_main(). */
- movl %ebx, %esp
-
- /* Get number of MTRRs. */
- popl %ebx
- movl $MTRRphysBase_MSR(0), %ecx
-1:
- testl %ebx, %ebx
- jz 1f
-
- /* Low 32 bits of MTRR base. */
- popl %eax
- /* Upper 32 bits of MTRR base. */
- popl %edx
- /* Write MTRR base. */
- wrmsr
- inc %ecx
- /* Low 32 bits of MTRR mask. */
- popl %eax
- /* Upper 32 bits of MTRR mask. */
- popl %edx
- /* Write MTRR mask. */
- wrmsr
- inc %ecx
-
- dec %ebx
- jmp 1b
-1:
- post_code(0x39)
-
- /* And enable cache again after setting MTRRs. */
- movl %cr0, %eax
- andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
- movl %eax, %cr0
-
- post_code(0x3a)
-
- /* Enable MTRR. */
- movl $MTRRdefType_MSR, %ecx
- rdmsr
- orl $MTRRdefTypeEn, %eax
- wrmsr
-
- post_code(0x3b)
-
- /* Invalidate the cache again. */
- invd
-
- post_code(0x3c)
-
-__main:
- post_code(POST_PREPARE_RAMSTAGE)
- cld /* Clear direction flag. */
- call romstage_after_car
-
-.Lhlt:
- post_code(POST_DEAD_CODE)
- hlt
- jmp .Lhlt
-
-mtrr_table:
- /* Fixed MTRRs */
- .word 0x250, 0x258, 0x259
- .word 0x268, 0x269, 0x26A
- .word 0x26B, 0x26C, 0x26D
- .word 0x26E, 0x26F
- /* Variable MTRRs */
- .word 0x200, 0x201, 0x202, 0x203
- .word 0x204, 0x205, 0x206, 0x207
- .word 0x208, 0x209, 0x20A, 0x20B
- .word 0x20C, 0x20D, 0x20E, 0x20F
- .word 0x210, 0x211, 0x212, 0x213
-mtrr_table_end:
-
diff --git a/src/soc/intel/skylake/romstage/cpu.c b/src/soc/intel/skylake/romstage/cpu.c
index af175be..ba472a9 100644
--- a/src/soc/intel/skylake/romstage/cpu.c
+++ b/src/soc/intel/skylake/romstage/cpu.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <arch/cpu.h>
@@ -34,7 +35,7 @@
{
msr_t msr, perf_ctl, platform_info;
- /* Check for configurable TDP option */
+ /* Check for configurable TDP option */
platform_info = rdmsr(MSR_PLATFORM_INFO);
if ((platform_info.hi >> 1) & 3) {
@@ -51,5 +52,5 @@
wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n",
- ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
+ ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
}
diff --git a/src/soc/intel/skylake/romstage/pch.c b/src/soc/intel/skylake/romstage/pch.c
index 6fa6c39..9ca83b3 100644
--- a/src/soc/intel/skylake/romstage/pch.c
+++ b/src/soc/intel/skylake/romstage/pch.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,10 +15,11 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <arch/io.h>
+#include <chip.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
@@ -25,97 +27,25 @@
#include <soc/iomap.h>
#include <soc/lpc.h>
#include <soc/pch.h>
+#include <soc/pcr.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
-#include <soc/rcba.h>
+#include <soc/pmc.h>
#include <soc/romstage.h>
#include <soc/smbus.h>
-#include <soc/intel/broadwell/chip.h>
-const struct reg_script pch_early_init_script[] = {
- /* Setup southbridge BARs */
- REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
- REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
- REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
- REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
- REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
+/* Max PXRC registers in ITSS*/
+#define MAX_PXRC_CONFIG 0x08
- /* Set COM1/COM2 decode range */
- REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
- /* Enable legacy decode ranges */
- REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
- COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
-
- /* Enable IOAPIC */
- REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
- /* Read back for posted write */
- REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
-
- /* Set HPET address and enable it */
- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
- /* Read back for posted write */
- REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
- /* Enable HPET to start counter */
- REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
-
- /* Disable reset */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
- /* TCO timer halt */
- REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
-
- /* Enable upper 128 bytes of CMOS */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
-
- /* Disable unused device (always) */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
-
- REG_SCRIPT_END
-};
-
-const struct reg_script pch_interrupt_init_script[] = {
- /*
- * GFX INTA -> PIRQA (MSI)
- * D28IP_P1IP PCIE INTA -> PIRQA
- * D29IP_E1P EHCI INTA -> PIRQD
- * D20IP_XHCI XHCI INTA -> PIRQC (MSI)
- * D31IP_SIP SATA INTA -> PIRQF (MSI)
- * D31IP_SMIP SMBUS INTB -> PIRQG
- * D31IP_TTIP THRT INTC -> PIRQA
- * D27IP_ZIP HDA INTA -> PIRQG (MSI)
- */
-
- /* Device interrupt pin register (board specific) */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IP,
- (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
- (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IP, (INTA << D29IP_E1P)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IP,
- (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
- (INTB << D28IP_P4IP)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IP, (INTA << D27IP_ZIP)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D26IP, (INTA << D26IP_E2P)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IP, (NOINT << D22IP_MEI1IP)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IP, (INTA << D20IP_XHCI)),
-
- /* Device interrupt route registers */
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D31IR, /* LPC */
- DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D29IR, /* EHCI */
- DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D28IR, /* PCIE */
- DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D27IR, /* HDA */
- DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D22IR, /* ME */
- DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D21IR, /* SIO */
- DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D20IR, /* XHCI */
- DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),
- REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + D23IR, /* SDIO */
- DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),
-
- REG_SCRIPT_END
+static const u8 pch_interrupt_routing[] = {
+ 11, /* PARC: PIRQA -> IRQ11 */
+ 10, /* PBRC: PIRQB -> IRQ10 */
+ 11, /* PCRC: PIRQC -> IRQ11 */
+ 11, /* PDRC: PIRQD -> IRQ11 */
+ 11, /* PERC: PIRQE -> IRQ11 */
+ 11, /* PFRC: PIRQF -> IRQ11 */
+ 11, /* PGRC: PIRQG -> IRQ11 */
+ 11 /* PHRC: PIRQH -> IRQ11 */
};
static void pch_enable_lpc(void)
@@ -123,39 +53,85 @@
/* Lookup device tree in romstage */
const struct device *dev;
const config_t *config;
+ u16 lpc_en;
+
+ /* IO Decode Range */
+ lpc_en = COMA_RANGE | (COMB_RANGE << 4);
+ pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, lpc_en);
+ pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOD, lpc_en);
+
+ /* IO Decode Enable */
+ lpc_en = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | GAMEH_LPC_EN |
+ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN;
+ pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_en);
+ pcr_write16(PID_DMI, R_PCH_PCR_DMI_LPCIOE, lpc_en);
dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
if (!dev || !dev->chip_info)
return;
config = dev->chip_info;
+ /* Set in PCI generic decode range registers */
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec);
+
+ /* Mirror these same settings in DMI PCR */
+ pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR1, config->gen1_dec);
+ pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR2, config->gen2_dec);
+ pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR3, config->gen3_dec);
+ pcr_write32(PID_DMI, R_PCH_PCR_DMI_LPCLGIR4, config->gen4_dec);
}
-static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or)
+static void pch_device_init(void)
{
+ device_t dev;
u32 reg32;
+ u16 tcobase;
+ u16 tcocnt;
- reg32 = pci_read_config32(dev, reg);
- reg32 &= mask;
- reg32 |= or;
- pci_write_config32(dev, reg, reg32);
+ dev = PCH_DEV_PMC;
+
+ /* Enable ACPI and PMC mmio regs in PMC Config */
+ reg32 = pci_read_config32(dev, ACTL);
+ reg32 |= ACPI_EN | PWRM_EN;
+ pci_write_config32(dev, ACTL, reg32);
+
+ /* TCO timer halt */
+ tcobase = pmc_tco_regs();
+ tcocnt = inw(tcobase + TCO1_CNT);
+ tcocnt |= TCO_TMR_HLT;
+ outw(tcocnt, tcobase + TCO1_CNT);
+
+ /* Enable upper 128 bytes of CMOS */
+ pcr_andthenor32(PID_RTC, R_PCH_PCR_RTC_CONF, (u32)~0,
+ B_PCH_PCR_RTC_CONF_UCMOS_EN);
+}
+
+static void pch_interrupt_init(void)
+{
+ u8 index = 0;
+
+ for (index = 0; index < MAX_PXRC_CONFIG; index++) {
+ if (pch_interrupt_routing[index] < 16 &&
+ pch_interrupt_routing[index] > 2 &&
+ pch_interrupt_routing[index] != 8 &&
+ pch_interrupt_routing[index] != 13) {
+ pcr_write8(PID_ITSS,
+ (R_PCH_PCR_ITSS_PIRQA_ROUT + index),
+ pch_interrupt_routing[index]);
+ }
+ }
}
void pch_early_init(void)
{
- reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
- reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);
+ pch_device_init();
+
+ pch_interrupt_init();
pch_enable_lpc();
enable_smbus();
-
- /* 8.14 Additional PCI Express Programming Steps, step #1 */
- pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0);
- pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80);
- pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30);
}
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index bdb3da9..7a6c8b3 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <arch/early_variables.h>
@@ -29,14 +30,14 @@
#include <stdlib.h>
#include <string.h>
#include <soc/iomap.h>
-#include <soc/lpc.h>
+#include <soc/pmc.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/romstage.h>
static struct chipset_power_state power_state CAR_GLOBAL;
-static void migrate_power_state(void)
+static void migrate_power_state(int is_recovery)
{
struct chipset_power_state *ps_cbmem;
struct chipset_power_state *ps_car;
@@ -50,7 +51,7 @@
}
memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem));
}
-CAR_MIGRATE(migrate_power_state);
+ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state)
/* Return 0, 3, or 5 to indicate the previous sleep state. */
static int prev_sleep_state(struct chipset_power_state *ps)
@@ -60,7 +61,7 @@
if (ps->pm1_sts & WAK_STS) {
switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
-#if CONFIG_HAVE_ACPI_RESUME
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
case SLP_TYP_S3:
prev_sleep_state = SLEEP_STATE_S3;
break;
@@ -73,7 +74,7 @@
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
}
- if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
prev_sleep_state = SLEEP_STATE_S5;
return prev_sleep_state;
@@ -94,8 +95,8 @@
ps->gpe0_en[0], ps->gpe0_en[1],
ps->gpe0_en[2], ps->gpe0_en[3]);
- printk(BIOS_DEBUG, "GEN_PMCON: %04x %04x %04x\n",
- ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
+ printk(BIOS_DEBUG, "GEN_PMCON: %04x %04x\n",
+ ps->gen_pmcon_a, ps->gen_pmcon_b);
printk(BIOS_DEBUG, "Previous Sleep State: S%d\n",
ps->prev_sleep_state);
@@ -104,13 +105,16 @@
/* Fill power state structure from ACPI PM registers */
struct chipset_power_state *fill_power_state(void)
{
+ uint16_t tcobase;
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+ tcobase = pmc_tco_regs();
+
ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
- ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
+ ps->tco1_sts = inw(tcobase + TCO1_STS);
+ ps->tco2_sts = inw(tcobase + TCO2_STS);
ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
@@ -120,9 +124,8 @@
ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
- ps->gen_pmcon1 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_1);
- ps->gen_pmcon2 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_2);
- ps->gen_pmcon3 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_3);
+ ps->gen_pmcon_a = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_A);
+ ps->gen_pmcon_b = pci_read_config16(PCH_DEV_PMC, GEN_PMCON_B);
ps->prev_sleep_state = prev_sleep_state(ps);
diff --git a/src/soc/intel/skylake/romstage/raminit.c b/src/soc/intel/skylake/romstage/raminit.c
deleted file mode 100644
index 52ea491..0000000
--- a/src/soc/intel/skylake/romstage/raminit.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/cbfs.h>
-#include <arch/io.h>
-#include <cbfs.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <device/pci_def.h>
-#include <lib.h>
-#include <string.h>
-#if CONFIG_EC_GOOGLE_CHROMEEC
-#include <ec/google/chromeec/ec.h>
-#include <ec/google/chromeec/ec_commands.h>
-#endif
-#include <stage_cache.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/intel/common/mrc_cache.h>
-#include <soc/iomap.h>
-#include <soc/pei_data.h>
-#include <soc/pei_wrapper.h>
-#include <soc/pm.h>
-#include <soc/reset.h>
-#include <soc/romstage.h>
-#include <soc/smm.h>
-#include <soc/systemagent.h>
-
-/*
- * Find PEI executable in coreboot filesystem and execute it.
- */
-void raminit(struct pei_data *pei_data)
-{
- const struct mrc_saved_data *cache;
- struct memory_info* mem_info;
- pei_wrapper_entry_t entry;
- int ret;
-
- broadwell_fill_pei_data(pei_data);
-
- if (recovery_mode_enabled()) {
- /* Recovery mode does not use MRC cache */
- printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n");
- } else if (!mrc_cache_get_current(&cache)) {
- /* MRC cache found */
- pei_data->saved_data_size = cache->size;
- pei_data->saved_data = &cache->data[0];
- } else if (pei_data->boot_mode == SLEEP_STATE_S3) {
- /* Waking from S3 and no cache. */
- printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
- post_code(POST_RESUME_FAILURE);
- reset_system();
- } else {
- printk(BIOS_DEBUG, "No MRC cache found.\n");
-#if CONFIG_EC_GOOGLE_CHROMEEC
- if (pei_data->boot_mode == SLEEP_STATE_S0) {
- /* Ensure EC is running RO firmware. */
- google_chromeec_check_ec_image(EC_IMAGE_RO);
- }
-#endif
- }
-
- /*
- * Do not use saved pei data. Can be set by mainboard romstage
- * to force a full train of memory on every boot.
- */
- if (pei_data->disable_saved_data) {
- printk(BIOS_DEBUG, "Disabling PEI saved data by request\n");
- pei_data->saved_data = NULL;
- pei_data->saved_data_size = 0;
- }
-
- /* Determine if mrc.bin is in the cbfs. */
- entry = (pei_wrapper_entry_t)cbfs_get_file_content(
- CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL);
- if (entry == NULL) {
- printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
- return;
- }
-
- printk(BIOS_DEBUG, "Starting Memory Reference Code\n");
-
- ret = entry(pei_data);
- if (ret < 0)
- die("pei_data version mismatch\n");
-
- /* Print the MRC version after executing the UEFI PEI stage. */
- u32 version = MCHBAR32(MCHBAR_PEI_VERSION);
- printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
- version >> 24 , (version >> 16) & 0xff,
- (version >> 8) & 0xff, version & 0xff);
-
- report_memory_config();
-
- /* Basic memory sanity test */
- quick_ram_check();
-
- if (pei_data->boot_mode != SLEEP_STATE_S3) {
- cbmem_initialize_empty();
- stage_cache_create_empty();
- } else {
- stage_cache_recover();
- if (cbmem_initialize()) {
-#if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
- /* Failed S3 resume, reset to come up cleanly */
- reset_system();
-#endif
- }
- }
-
- printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save,
- pei_data->data_to_save_size);
-
- if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0)
- mrc_cache_stash_data(pei_data->data_to_save,
- pei_data->data_to_save_size);
-
- printk(BIOS_DEBUG, "create cbmem for dimm information\n");
- mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
- memcpy(mem_info, &pei_data->meminfo, sizeof(struct memory_info));
-
-}
diff --git a/src/soc/intel/skylake/romstage/report_platform.c b/src/soc/intel/skylake/romstage/report_platform.c
index 713b3e7..fe1a785 100644
--- a/src/soc/intel/skylake/romstage/report_platform.c
+++ b/src/soc/intel/skylake/romstage/report_platform.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,77 +15,55 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <arch/cpu.h>
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
#include <cpu/x86/msr.h>
+#include <device/pci.h>
#include <soc/cpu.h>
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/systemagent.h>
+#include <string.h>
static struct {
u32 cpuid;
const char *name;
} cpu_table[] = {
- { CPUID_HASWELL_A0, "Haswell A0" },
- { CPUID_HASWELL_B0, "Haswell B0" },
- { CPUID_HASWELL_C0, "Haswell C0" },
- { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" },
- { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" },
- { CPUID_HASWELL_HALO, "Haswell Perf Halo" },
- { CPUID_BROADWELL_C0, "Broadwell C0" },
- { CPUID_BROADWELL_D0, "Broadwell D0" },
- { CPUID_BROADWELL_E0, "Broadwell E0 or F0" },
+ { CPUID_SKYLAKE_C0, "Skylake C0" },
+ { CPUID_SKYLAKE_D0, "Skylake D0" },
};
static struct {
- u8 revid;
+ u16 mchid;
const char *name;
-} mch_rev_table[] = {
- { MCH_BROADWELL_REV_D0, "Broadwell D0" },
- { MCH_BROADWELL_REV_E0, "Broadwell E0" },
- { MCH_BROADWELL_REV_F0, "Broadwell F0" },
+} mch_table[] = {
+ { MCH_SKYLAKE_ID_U, "Skylake-U" },
+ { MCH_SKYLAKE_ID_Y, "Skylake-Y" },
+ { MCH_SKYLAKE_ID_ULX, "Skylake-ULX" },
};
static struct {
u16 lpcid;
const char *name;
} pch_table[] = {
- { PCH_LPT_LP_SAMPLE, "LynxPoint LP Sample" },
- { PCH_LPT_LP_PREMIUM, "LynxPoint LP Premium" },
- { PCH_LPT_LP_MAINSTREAM, "LynxPoint LP Mainstream" },
- { PCH_LPT_LP_VALUE, "LynxPoint LP Value" },
- { PCH_WPT_HSW_U_SAMPLE, "Haswell U Sample" },
- { PCH_WPT_BDW_U_SAMPLE, "Broadwell U Sample" },
- { PCH_WPT_BDW_U_PREMIUM, "Broadwell U Premium" },
- { PCH_WPT_BDW_U_BASE, "Broadwell U Base" },
- { PCH_WPT_BDW_Y_SAMPLE, "Broadwell Y Sample" },
- { PCH_WPT_BDW_Y_PREMIUM, "Broadwell Y Premium" },
- { PCH_WPT_BDW_Y_BASE, "Broadwell Y Base" },
- { PCH_WPT_BDW_H, "Broadwell H" },
+ { PCH_SPT_LP_SAMPLE, "Skylake LP Sample" },
+ { PCH_SPT_LP_U_BASE, "Skylake-U Base" },
+ { PCH_SPT_LP_U_PREMIUM, "Skylake-U Premium" },
+ { PCH_SPT_LP_Y_PREMIUM, "Skylake-Y Premium" },
};
static struct {
u16 igdid;
const char *name;
} igd_table[] = {
- { IGD_HASWELL_ULT_GT1, "Haswell ULT GT1" },
- { IGD_HASWELL_ULT_GT2, "Haswell ULT GT2" },
- { IGD_HASWELL_ULT_GT3, "Haswell ULT GT3" },
- { IGD_BROADWELL_U_GT1, "Broadwell U GT1" },
- { IGD_BROADWELL_U_GT2, "Broadwell U GT2" },
- { IGD_BROADWELL_U_GT3_15W, "Broadwell U GT3 (15W)" },
- { IGD_BROADWELL_U_GT3_28W, "Broadwell U GT3 (28W)" },
- { IGD_BROADWELL_Y_GT2, "Broadwell Y GT2" },
- { IGD_BROADWELL_H_GT2, "Broadwell U GT2" },
- { IGD_BROADWELL_H_GT3, "Broadwell U GT3" },
+ { IGD_SKYLAKE_GT1_SULTM, "Skylake ULT GT1"},
+ { IGD_SKYLAKE_GT2_SULXM, "Skylake ULX GT2" },
+ { IGD_SKYLAKE_GT2_SULTM, "Skylake ULT GT2" },
};
static void report_cpu_info(void)
@@ -102,8 +81,8 @@
if (cpuidr.eax < 0x80000004) {
strcpy(cpu_string, "Platform info not available");
} else {
- u32 *p = (u32*) cpu_string;
- for (i = 2; i <= 4 ; i++) {
+ u32 *p = (u32 *) cpu_string;
+ for (i = 2; i <= 4; i++) {
cpuidr = cpuid(index + i);
*p++ = cpuidr.eax;
*p++ = cpuidr.ebx;
@@ -136,29 +115,27 @@
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
- printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, "
- "VT %ssupported\n", mode[aes], mode[txt], mode[vt]);
+ printk(BIOS_DEBUG,
+ "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
}
static void report_mch_info(void)
{
int i;
- u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
+ u16 mchid = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID);
u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID);
const char *mch_type = "Unknown";
- /* Look for string to match the revision for Broadwell U/Y */
- if (mch_device == MCH_BROADWELL_ID_U_Y) {
- for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) {
- if (mch_rev_table[i].revid == mch_revision) {
- mch_type = mch_rev_table[i].name;
- break;
- }
+ for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
+ if (mch_table[i].mchid == mchid) {
+ mch_type = mch_table[i].name;
+ break;
}
}
printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
- mch_device, mch_revision, mch_type);
+ mchid, mch_revision, mch_type);
}
static void report_pch_info(void)
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index c026004..e8bb877 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <stddef.h>
@@ -24,141 +25,542 @@
#include <arch/cbfs.h>
#include <arch/stages.h>
#include <arch/early_variables.h>
-#include <console/console.h>
-#include <cbfs.h>
#include <cbmem.h>
+#include <chip.h>
+#include <console/console.h>
#include <cpu/x86/mtrr.h>
+#include <device/device.h>
+#include <device/pci_def.h>
#include <elog.h>
+#include <reset.h>
#include <romstage_handoff.h>
-#include <stage_cache.h>
-#include <timestamp.h>
-#include <soc/me.h>
-#include <soc/pei_data.h>
+#include <soc/pci_devs.h>
+#include <soc/pei_wrapper.h>
#include <soc/pm.h>
-#include <soc/reset.h>
+#include <soc/serialio.h>
#include <soc/romstage.h>
#include <soc/spi.h>
+#include <stage_cache.h>
+#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
-/* Entry from cache-as-ram.inc. */
-void * asmlinkage romstage_main(unsigned long bist,
- uint32_t tsc_low, uint32_t tsc_hi)
+/* SOC initialization before the console is enabled */
+void soc_pre_console_init(struct romstage_params *params)
{
- struct romstage_params rp = {
- .bist = bist,
- .pei_data = NULL,
- };
-
- post_code(0x30);
-
- /* Save initial timestamp from bootblock. */
- timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low);
-
- /* Save romstage begin */
- timestamp_add_now(TS_START_ROMSTAGE);
-
/* System Agent Early Initialization */
systemagent_early_init();
- /* PCH Early Initialization */
+ if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
+ pch_uart_init();
+}
+
+/* SOC initialization before RAM is enabled */
+void soc_pre_ram_init(struct romstage_params *params)
+{
+ /* Prepare to initialize memory */
+ soc_fill_pei_data(params->pei_data);
+}
+
+void soc_romstage_init(struct romstage_params *params)
+{
pch_early_init();
-
- /* Call into mainboard pre console init. Needed to enable serial port
- on IT8772 */
- mainboard_pre_console_init();
-
- /* Start console drivers */
- console_init();
-
- /* Get power state */
- rp.power_state = fill_power_state();
-
- /* Print useful platform information */
- report_platform_info();
-
- /* Set CPU frequency to maximum */
- set_max_freq();
-
- /* Call into mainboard. */
- mainboard_romstage_entry(&rp);
-
-#if CONFIG_CHROMEOS
- save_chromeos_gpios();
-#endif
-
- return setup_stack_and_mttrs();
}
-static inline void chromeos_init(int prev_sleep_state)
-{
-#if CONFIG_CHROMEOS
- /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */
- init_chromeos(prev_sleep_state == SLEEP_STATE_S3 ? 2 : 0);
-#endif
-}
-
-/* Entry from the mainboard. */
-void romstage_common(struct romstage_params *params)
-{
- struct romstage_handoff *handoff;
-
- post_code(0x32);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
-
- params->pei_data->boot_mode = params->power_state->prev_sleep_state;
-
-#if CONFIG_ELOG_BOOT_COUNT
- if (params->power_state->prev_sleep_state != SLEEP_STATE_S3)
- boot_count_increment();
-#endif
-
- /* Print ME state before MRC */
- intel_me_status();
-
- /* Save ME HSIO version */
- intel_me_hsio_version(¶ms->power_state->hsio_version,
- ¶ms->power_state->hsio_checksum);
-
- /* Initialize RAM */
- raminit(params->pei_data);
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- handoff = romstage_handoff_find_or_add();
- if (handoff != NULL)
- handoff->s3_resume = (params->power_state->prev_sleep_state ==
- SLEEP_STATE_S3);
- else
- printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
-
- chromeos_init(params->power_state->prev_sleep_state);
-}
-
-void asmlinkage romstage_after_car(void)
-{
- timestamp_add_now(TS_END_ROMSTAGE);
-
- /* Load the ramstage. */
- copy_and_run();
- while (1);
-}
-
-void ramstage_cache_invalid(void)
-{
-#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE
- /* Perform cold reset on invalid ramstage cache. */
- reset_system();
-#endif
-}
-
-#if CONFIG_CHROMEOS
+#if IS_ENABLED(CONFIG_CHROMEOS)
int vboot_get_sw_write_protect(void)
{
u8 status;
+
/* Return unprotected status if status read fails. */
- return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80));
+ return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80);
+}
+#endif
+
+/* UPD parameters to be initialized before MemoryInit */
+void soc_memory_init_params(MEMORY_INIT_UPD *params)
+{
+ const struct device *dev;
+ const struct soc_intel_skylake_config *config;
+ int i;
+
+ /* Set the parameters for MemoryInit */
+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ config = dev->chip_info;
+
+ for (i = 0; i < PchSerialIoIndexMax; i++)
+ params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+
+ params->MmioSize = 0x800; /* 2GB in MB */
+ params->TsegSize = CONFIG_SMM_TSEG_SIZE;
+ params->IedSize = config->IedSize;
+ params->ProbelessTrace = config->ProbelessTrace;
+ params->EnableLan = config->EnableLan;
+ params->EnableSata = config->EnableSata;
+ params->SataMode = config->SataMode;
+ params->SataSalpSupport = config->SataSalpSupport;
+ params->SataPortsEnable[0] = config->SataPortsEnable[0];
+ params->SsicPortEnable = config->SsicPortEnable;
+ params->EnableTraceHub = config->EnableTraceHub;
+ params->SmbusEnable = config->SmbusEnable;
+ params->Cio2Enable = config->Cio2Enable;
+ params->ScsEmmcEnabled = config->ScsEmmcEnabled;
+ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+ params->ScsSdCardEnabled = config->ScsSdCardEnabled;
+ params->IshEnable = 0;
+ params->EnableAzalia = config->EnableAzalia;
+ params->IoBufferOwnership = config->IoBufferOwnership;
+ params->DspEnable = config->DspEnable;
+ params->XdciEnable = config->XdciEnable;
}
-#endif
-void __attribute__((weak)) mainboard_pre_console_init(void) {}
+void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
+ MEMORY_INIT_UPD *new)
+{
+ /* Display the parameters for MemoryInit */
+ printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
+
+ soc_display_upd_value("PlatformMemorySize", 8,
+ old->PlatformMemorySize, new->PlatformMemorySize);
+ soc_display_upd_value("MemorySpdPtr00", 4, old->MemorySpdPtr00,
+ new->MemorySpdPtr00);
+ soc_display_upd_value("MemorySpdPtr01", 4, old->MemorySpdPtr01,
+ new->MemorySpdPtr01);
+ soc_display_upd_value("MemorySpdPtr10", 4, old->MemorySpdPtr10,
+ new->MemorySpdPtr10);
+ soc_display_upd_value("MemorySpdPtr11", 4, old->MemorySpdPtr11,
+ new->MemorySpdPtr11);
+ soc_display_upd_value("MemorySpdDataLen", 2, old->MemorySpdDataLen,
+ new->MemorySpdDataLen);
+ soc_display_upd_value("DqByteMapCh0[0]", 1, old->DqByteMapCh0[0],
+ new->DqByteMapCh0[0]);
+ soc_display_upd_value("DqByteMapCh0[1]", 1, old->DqByteMapCh0[1],
+ new->DqByteMapCh0[1]);
+ soc_display_upd_value("DqByteMapCh0[2]", 1, old->DqByteMapCh0[2],
+ new->DqByteMapCh0[2]);
+ soc_display_upd_value("DqByteMapCh0[3]", 1, old->DqByteMapCh0[3],
+ new->DqByteMapCh0[3]);
+ soc_display_upd_value("DqByteMapCh0[4]", 1, old->DqByteMapCh0[4],
+ new->DqByteMapCh0[4]);
+ soc_display_upd_value("DqByteMapCh0[5]", 1, old->DqByteMapCh0[5],
+ new->DqByteMapCh0[5]);
+ soc_display_upd_value("DqByteMapCh0[6]", 1, old->DqByteMapCh0[6],
+ new->DqByteMapCh0[6]);
+ soc_display_upd_value("DqByteMapCh0[7]", 1, old->DqByteMapCh0[7],
+ new->DqByteMapCh0[7]);
+ soc_display_upd_value("DqByteMapCh0[8]", 1, old->DqByteMapCh0[8],
+ new->DqByteMapCh0[8]);
+ soc_display_upd_value("DqByteMapCh0[9]", 1, old->DqByteMapCh0[9],
+ new->DqByteMapCh0[9]);
+ soc_display_upd_value("DqByteMapCh0[10]", 1, old->DqByteMapCh0[10],
+ new->DqByteMapCh0[10]);
+ soc_display_upd_value("DqByteMapCh0[11]", 1, old->DqByteMapCh0[11],
+ new->DqByteMapCh0[11]);
+ soc_display_upd_value("DqByteMapCh1[0]", 1, old->DqByteMapCh1[0],
+ new->DqByteMapCh1[0]);
+ soc_display_upd_value("DqByteMapCh1[1]", 1, old->DqByteMapCh1[1],
+ new->DqByteMapCh1[1]);
+ soc_display_upd_value("DqByteMapCh1[2]", 1, old->DqByteMapCh1[2],
+ new->DqByteMapCh1[2]);
+ soc_display_upd_value("DqByteMapCh1[3]", 1, old->DqByteMapCh1[3],
+ new->DqByteMapCh1[3]);
+ soc_display_upd_value("DqByteMapCh1[4]", 1, old->DqByteMapCh1[4],
+ new->DqByteMapCh1[4]);
+ soc_display_upd_value("DqByteMapCh1[5]", 1, old->DqByteMapCh1[5],
+ new->DqByteMapCh1[5]);
+ soc_display_upd_value("DqByteMapCh1[6]", 1, old->DqByteMapCh1[6],
+ new->DqByteMapCh1[6]);
+ soc_display_upd_value("DqByteMapCh1[7]", 1, old->DqByteMapCh1[7],
+ new->DqByteMapCh1[7]);
+ soc_display_upd_value("DqByteMapCh1[8]", 1, old->DqByteMapCh1[8],
+ new->DqByteMapCh1[8]);
+ soc_display_upd_value("DqByteMapCh1[9]", 1, old->DqByteMapCh1[9],
+ new->DqByteMapCh1[9]);
+ soc_display_upd_value("DqByteMapCh1[10]", 1, old->DqByteMapCh1[10],
+ new->DqByteMapCh1[10]);
+ soc_display_upd_value("DqByteMapCh1[11]", 1, old->DqByteMapCh1[11],
+ new->DqByteMapCh1[11]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[0]", 1,
+ old->DqsMapCpu2DramCh0[0], new->DqsMapCpu2DramCh0[0]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[1]", 1,
+ old->DqsMapCpu2DramCh0[1], new->DqsMapCpu2DramCh0[1]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[2]", 1,
+ old->DqsMapCpu2DramCh0[2], new->DqsMapCpu2DramCh0[2]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[3]", 1,
+ old->DqsMapCpu2DramCh0[3], new->DqsMapCpu2DramCh0[3]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[4]", 1,
+ old->DqsMapCpu2DramCh0[4], new->DqsMapCpu2DramCh0[4]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[5]", 1,
+ old->DqsMapCpu2DramCh0[5], new->DqsMapCpu2DramCh0[5]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[6]", 1,
+ old->DqsMapCpu2DramCh0[6], new->DqsMapCpu2DramCh0[6]);
+ soc_display_upd_value("DqsMapCpu2DramCh0[7]", 1,
+ old->DqsMapCpu2DramCh0[7], new->DqsMapCpu2DramCh0[7]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[0]", 1,
+ old->DqsMapCpu2DramCh1[0], new->DqsMapCpu2DramCh1[0]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[1]", 1,
+ old->DqsMapCpu2DramCh1[1], new->DqsMapCpu2DramCh1[1]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[2]", 1,
+ old->DqsMapCpu2DramCh1[2], new->DqsMapCpu2DramCh1[2]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[3]", 1,
+ old->DqsMapCpu2DramCh1[3], new->DqsMapCpu2DramCh1[3]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[4]", 1,
+ old->DqsMapCpu2DramCh1[4], new->DqsMapCpu2DramCh1[4]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[5]", 1,
+ old->DqsMapCpu2DramCh1[5], new->DqsMapCpu2DramCh1[5]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[6]", 1,
+ old->DqsMapCpu2DramCh1[6], new->DqsMapCpu2DramCh1[6]);
+ soc_display_upd_value("DqsMapCpu2DramCh1[7]", 1,
+ old->DqsMapCpu2DramCh1[7], new->DqsMapCpu2DramCh1[7]);
+ soc_display_upd_value("DqPinsInterleaved", 1,
+ old->DqPinsInterleaved, new->DqPinsInterleaved);
+ soc_display_upd_value("RcompResistor[0]", 2, old->RcompResistor[0],
+ new->RcompResistor[0]);
+ soc_display_upd_value("RcompResistor[1]", 2, old->RcompResistor[1],
+ new->RcompResistor[1]);
+ soc_display_upd_value("RcompResistor[2]", 2, old->RcompResistor[2],
+ new->RcompResistor[2]);
+ soc_display_upd_value("RcompTarget[0]", 1, old->RcompTarget[0],
+ new->RcompTarget[0]);
+ soc_display_upd_value("RcompTarget[1]", 1, old->RcompTarget[1],
+ new->RcompTarget[1]);
+ soc_display_upd_value("RcompTarget[2]", 1, old->RcompTarget[2],
+ new->RcompTarget[2]);
+ soc_display_upd_value("RcompTarget[3]", 1, old->RcompTarget[3],
+ new->RcompTarget[3]);
+ soc_display_upd_value("RcompTarget[4]", 1, old->RcompTarget[4],
+ new->RcompTarget[4]);
+ soc_display_upd_value("CaVrefConfig", 1, old->CaVrefConfig,
+ new->CaVrefConfig);
+ soc_display_upd_value("SmramMask", 1, old->SmramMask, new->SmramMask);
+ soc_display_upd_value("MrcFastBoot", 1, old->MrcFastBoot,
+ new->MrcFastBoot);
+ soc_display_upd_value("IedSize", 4, old->IedSize, new->IedSize);
+ soc_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize);
+ soc_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize);
+ soc_display_upd_value("ProbelessTrace", 1, old->ProbelessTrace,
+ new->ProbelessTrace);
+ soc_display_upd_value("EnableLan", 1, old->EnableLan, new->EnableLan);
+ soc_display_upd_value("EnableSata", 1, old->EnableSata,
+ new->EnableSata);
+ soc_display_upd_value("SataMode", 1, old->SataMode, new->SataMode);
+ soc_display_upd_value("SataSalpSupport", 1, old->SataSalpSupport,
+ new->SataSalpSupport);
+ soc_display_upd_value("SataPortsEnable[0]", 1, old->SataPortsEnable[0],
+ new->SataPortsEnable[0]);
+ soc_display_upd_value("SataPortsEnable[1]", 1, old->SataPortsEnable[1],
+ new->SataPortsEnable[1]);
+ soc_display_upd_value("SataPortsEnable[2]", 1, old->SataPortsEnable[2],
+ new->SataPortsEnable[2]);
+ soc_display_upd_value("SataPortsEnable[3]", 1, old->SataPortsEnable[3],
+ new->SataPortsEnable[3]);
+ soc_display_upd_value("SataPortsEnable[4]", 1, old->SataPortsEnable[4],
+ new->SataPortsEnable[4]);
+ soc_display_upd_value("SataPortsEnable[5]", 1, old->SataPortsEnable[5],
+ new->SataPortsEnable[5]);
+ soc_display_upd_value("SataPortsEnable[6]", 1, old->SataPortsEnable[6],
+ new->SataPortsEnable[6]);
+ soc_display_upd_value("SataPortsEnable[7]", 1, old->SataPortsEnable[7],
+ new->SataPortsEnable[7]);
+ soc_display_upd_value("SataPortsDevSlp[0]", 1, old->SataPortsDevSlp[0],
+ new->SataPortsDevSlp[0]);
+ soc_display_upd_value("SataPortsDevSlp[1]", 1, old->SataPortsDevSlp[1],
+ new->SataPortsDevSlp[1]);
+ soc_display_upd_value("SataPortsDevSlp[2]", 1, old->SataPortsDevSlp[2],
+ new->SataPortsDevSlp[2]);
+ soc_display_upd_value("SataPortsDevSlp[3]", 1, old->SataPortsDevSlp[3],
+ new->SataPortsDevSlp[3]);
+ soc_display_upd_value("SataPortsDevSlp[4]", 1, old->SataPortsDevSlp[4],
+ new->SataPortsDevSlp[4]);
+ soc_display_upd_value("SataPortsDevSlp[5]", 1, old->SataPortsDevSlp[5],
+ new->SataPortsDevSlp[5]);
+ soc_display_upd_value("SataPortsDevSlp[6]", 1, old->SataPortsDevSlp[6],
+ new->SataPortsDevSlp[6]);
+ soc_display_upd_value("SataPortsDevSlp[7]", 1, old->SataPortsDevSlp[7],
+ new->SataPortsDevSlp[7]);
+ soc_display_upd_value("EnableAzalia", 1, old->EnableAzalia,
+ new->EnableAzalia);
+ soc_display_upd_value("DspEnable", 1, old->DspEnable, new->DspEnable);
+ soc_display_upd_value("IoBufferOwnership", 1, old->IoBufferOwnership,
+ new->IoBufferOwnership);
+ soc_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub,
+ new->EnableTraceHub);
+ soc_display_upd_value("PcieRpEnable[0]", 1, old->PcieRpEnable[0],
+ new->PcieRpEnable[0]);
+ soc_display_upd_value("PcieRpEnable[1]", 1, old->PcieRpEnable[1],
+ new->PcieRpEnable[1]);
+ soc_display_upd_value("PcieRpEnable[2]", 1, old->PcieRpEnable[2],
+ new->PcieRpEnable[2]);
+ soc_display_upd_value("PcieRpEnable[3]", 1, old->PcieRpEnable[3],
+ new->PcieRpEnable[3]);
+ soc_display_upd_value("PcieRpEnable[4]", 1, old->PcieRpEnable[4],
+ new->PcieRpEnable[4]);
+ soc_display_upd_value("PcieRpEnable[5]", 1, old->PcieRpEnable[5],
+ new->PcieRpEnable[5]);
+ soc_display_upd_value("PcieRpEnable[6]", 1, old->PcieRpEnable[6],
+ new->PcieRpEnable[6]);
+ soc_display_upd_value("PcieRpEnable[7]", 1, old->PcieRpEnable[7],
+ new->PcieRpEnable[7]);
+ soc_display_upd_value("PcieRpEnable[8]", 1, old->PcieRpEnable[8],
+ new->PcieRpEnable[8]);
+ soc_display_upd_value("PcieRpEnable[9]", 1, old->PcieRpEnable[9],
+ new->PcieRpEnable[9]);
+ soc_display_upd_value("PcieRpEnable[10]", 1, old->PcieRpEnable[10],
+ new->PcieRpEnable[10]);
+ soc_display_upd_value("PcieRpEnable[11]", 1, old->PcieRpEnable[11],
+ new->PcieRpEnable[11]);
+ soc_display_upd_value("PcieRpEnable[12]", 1, old->PcieRpEnable[12],
+ new->PcieRpEnable[12]);
+ soc_display_upd_value("PcieRpEnable[13]", 1, old->PcieRpEnable[13],
+ new->PcieRpEnable[13]);
+ soc_display_upd_value("PcieRpEnable[14]", 1, old->PcieRpEnable[14],
+ new->PcieRpEnable[14]);
+ soc_display_upd_value("PcieRpEnable[15]", 1, old->PcieRpEnable[15],
+ new->PcieRpEnable[15]);
+ soc_display_upd_value("PcieRpEnable[16]", 1, old->PcieRpEnable[16],
+ new->PcieRpEnable[16]);
+ soc_display_upd_value("PcieRpEnable[17]", 1, old->PcieRpEnable[17],
+ new->PcieRpEnable[17]);
+ soc_display_upd_value("PcieRpEnable[18]", 1, old->PcieRpEnable[18],
+ new->PcieRpEnable[18]);
+ soc_display_upd_value("PcieRpEnable[19]", 1, old->PcieRpEnable[19],
+ new->PcieRpEnable[19]);
+ soc_display_upd_value("PcieRpClkReqSupport[0]", 1,
+ old->PcieRpClkReqSupport[0],
+ new->PcieRpClkReqSupport[0]);
+ soc_display_upd_value("PcieRpClkReqSupport[1]", 1,
+ old->PcieRpClkReqSupport[1],
+ new->PcieRpClkReqSupport[1]);
+ soc_display_upd_value("PcieRpClkReqSupport[2]", 1,
+ old->PcieRpClkReqSupport[2],
+ new->PcieRpClkReqSupport[2]);
+ soc_display_upd_value("PcieRpClkReqSupport[3]", 1,
+ old->PcieRpClkReqSupport[3],
+ new->PcieRpClkReqSupport[3]);
+ soc_display_upd_value("PcieRpClkReqSupport[4]", 1,
+ old->PcieRpClkReqSupport[4],
+ new->PcieRpClkReqSupport[4]);
+ soc_display_upd_value("PcieRpClkReqSupport[5]", 1,
+ old->PcieRpClkReqSupport[5],
+ new->PcieRpClkReqSupport[5]);
+ soc_display_upd_value("PcieRpClkReqSupport[6]", 1,
+ old->PcieRpClkReqSupport[6],
+ new->PcieRpClkReqSupport[6]);
+ soc_display_upd_value("PcieRpClkReqSupport[7]", 1,
+ old->PcieRpClkReqSupport[7],
+ new->PcieRpClkReqSupport[7]);
+ soc_display_upd_value("PcieRpClkReqSupport[8]", 1,
+ old->PcieRpClkReqSupport[8],
+ new->PcieRpClkReqSupport[8]);
+ soc_display_upd_value("PcieRpClkReqSupport[9]", 1,
+ old->PcieRpClkReqSupport[9],
+ new->PcieRpClkReqSupport[9]);
+ soc_display_upd_value("PcieRpClkReqSupport[10]", 1,
+ old->PcieRpClkReqSupport[10],
+ new->PcieRpClkReqSupport[10]);
+ soc_display_upd_value("PcieRpClkReqSupport[11]", 1,
+ old->PcieRpClkReqSupport[11],
+ new->PcieRpClkReqSupport[11]);
+ soc_display_upd_value("PcieRpClkReqSupport[12]", 1,
+ old->PcieRpClkReqSupport[12],
+ new->PcieRpClkReqSupport[12]);
+ soc_display_upd_value("PcieRpClkReqSupport[13]", 1,
+ old->PcieRpClkReqSupport[13],
+ new->PcieRpClkReqSupport[13]);
+ soc_display_upd_value("PcieRpClkReqSupport[14]", 1,
+ old->PcieRpClkReqSupport[14],
+ new->PcieRpClkReqSupport[14]);
+ soc_display_upd_value("PcieRpClkReqSupport[15]", 1,
+ old->PcieRpClkReqSupport[15],
+ new->PcieRpClkReqSupport[15]);
+ soc_display_upd_value("PcieRpClkReqSupport[16]", 1,
+ old->PcieRpClkReqSupport[16],
+ new->PcieRpClkReqSupport[16]);
+ soc_display_upd_value("PcieRpClkReqSupport[17]", 1,
+ old->PcieRpClkReqSupport[17],
+ new->PcieRpClkReqSupport[17]);
+ soc_display_upd_value("PcieRpClkReqSupport[18]", 1,
+ old->PcieRpClkReqSupport[18],
+ new->PcieRpClkReqSupport[18]);
+ soc_display_upd_value("PcieRpClkReqSupport[19]", 1,
+ old->PcieRpClkReqSupport[19],
+ new->PcieRpClkReqSupport[19]);
+ soc_display_upd_value("PcieRpClkReqNumber[0]", 1,
+ old->PcieRpClkReqNumber[0],
+ new->PcieRpClkReqNumber[0]);
+ soc_display_upd_value("PcieRpClkReqNumber[1]", 1,
+ old->PcieRpClkReqNumber[1],
+ new->PcieRpClkReqNumber[1]);
+ soc_display_upd_value("PcieRpClkReqNumber[2]", 1,
+ old->PcieRpClkReqNumber[2],
+ new->PcieRpClkReqNumber[2]);
+ soc_display_upd_value("PcieRpClkReqNumber[3]", 1,
+ old->PcieRpClkReqNumber[3],
+ new->PcieRpClkReqNumber[3]);
+ soc_display_upd_value("PcieRpClkReqNumber[4]", 1,
+ old->PcieRpClkReqNumber[4],
+ new->PcieRpClkReqNumber[4]);
+ soc_display_upd_value("PcieRpClkReqNumber[5]", 1,
+ old->PcieRpClkReqNumber[5],
+ new->PcieRpClkReqNumber[5]);
+ soc_display_upd_value("PcieRpClkReqNumber[6]", 1,
+ old->PcieRpClkReqNumber[6],
+ new->PcieRpClkReqNumber[6]);
+ soc_display_upd_value("PcieRpClkReqNumber[7]", 1,
+ old->PcieRpClkReqNumber[7],
+ new->PcieRpClkReqNumber[7]);
+ soc_display_upd_value("PcieRpClkReqNumber[8]", 1,
+ old->PcieRpClkReqNumber[8],
+ new->PcieRpClkReqNumber[8]);
+ soc_display_upd_value("PcieRpClkReqNumber[9]", 1,
+ old->PcieRpClkReqNumber[9],
+ new->PcieRpClkReqNumber[9]);
+ soc_display_upd_value("PcieRpClkReqNumber[10]", 1,
+ old->PcieRpClkReqNumber[10],
+ new->PcieRpClkReqNumber[10]);
+ soc_display_upd_value("PcieRpClkReqNumber[11]", 1,
+ old->PcieRpClkReqNumber[11],
+ new->PcieRpClkReqNumber[11]);
+ soc_display_upd_value("PcieRpClkReqNumber[12]", 1,
+ old->PcieRpClkReqNumber[12],
+ new->PcieRpClkReqNumber[12]);
+ soc_display_upd_value("PcieRpClkReqNumber[13]", 1,
+ old->PcieRpClkReqNumber[13],
+ new->PcieRpClkReqNumber[13]);
+ soc_display_upd_value("PcieRpClkReqNumber[14]", 1,
+ old->PcieRpClkReqNumber[14],
+ new->PcieRpClkReqNumber[14]);
+ soc_display_upd_value("PcieRpClkReqNumber[15]", 1,
+ old->PcieRpClkReqNumber[15],
+ new->PcieRpClkReqNumber[15]);
+ soc_display_upd_value("PcieRpClkReqNumber[16]", 1,
+ old->PcieRpClkReqNumber[16],
+ new->PcieRpClkReqNumber[16]);
+ soc_display_upd_value("PcieRpClkReqNumber[17]", 1,
+ old->PcieRpClkReqNumber[17],
+ new->PcieRpClkReqNumber[17]);
+ soc_display_upd_value("PcieRpClkReqNumber[18]", 1,
+ old->PcieRpClkReqNumber[18],
+ new->PcieRpClkReqNumber[18]);
+ soc_display_upd_value("PcieRpClkReqNumber[19]", 1,
+ old->PcieRpClkReqNumber[19],
+ new->PcieRpClkReqNumber[19]);
+ soc_display_upd_value("PortUsb20Enable[0]", 1, old->PortUsb20Enable[0],
+ new->PortUsb20Enable[0]);
+ soc_display_upd_value("PortUsb20Enable[1]", 1, old->PortUsb20Enable[1],
+ new->PortUsb20Enable[1]);
+ soc_display_upd_value("PortUsb20Enable[2]", 1, old->PortUsb20Enable[2],
+ new->PortUsb20Enable[2]);
+ soc_display_upd_value("PortUsb20Enable[3]", 1, old->PortUsb20Enable[3],
+ new->PortUsb20Enable[3]);
+ soc_display_upd_value("PortUsb20Enable[4]", 1, old->PortUsb20Enable[4],
+ new->PortUsb20Enable[4]);
+ soc_display_upd_value("PortUsb20Enable[5]", 1, old->PortUsb20Enable[5],
+ new->PortUsb20Enable[5]);
+ soc_display_upd_value("PortUsb20Enable[6]", 1, old->PortUsb20Enable[6],
+ new->PortUsb20Enable[6]);
+ soc_display_upd_value("PortUsb20Enable[7]", 1, old->PortUsb20Enable[7],
+ new->PortUsb20Enable[7]);
+ soc_display_upd_value("PortUsb20Enable[8]", 1, old->PortUsb20Enable[8],
+ new->PortUsb20Enable[8]);
+ soc_display_upd_value("PortUsb20Enable[9]", 1, old->PortUsb20Enable[9],
+ new->PortUsb20Enable[9]);
+ soc_display_upd_value("PortUsb20Enable[10]", 1,
+ old->PortUsb20Enable[10],
+ new->PortUsb20Enable[10]);
+ soc_display_upd_value("PortUsb20Enable[11]", 1,
+ old->PortUsb20Enable[11],
+ new->PortUsb20Enable[11]);
+ soc_display_upd_value("PortUsb20Enable[12]", 1,
+ old->PortUsb20Enable[12],
+ new->PortUsb20Enable[12]);
+ soc_display_upd_value("PortUsb20Enable[13]", 1,
+ old->PortUsb20Enable[13],
+ new->PortUsb20Enable[13]);
+ soc_display_upd_value("PortUsb20Enable[14]", 1,
+ old->PortUsb20Enable[14],
+ new->PortUsb20Enable[14]);
+ soc_display_upd_value("PortUsb20Enable[15]", 1,
+ old->PortUsb20Enable[15],
+ new->PortUsb20Enable[15]);
+ soc_display_upd_value("PortUsb30Enable[0]", 1, old->PortUsb30Enable[0],
+ new->PortUsb30Enable[0]);
+ soc_display_upd_value("PortUsb30Enable[1]", 1, old->PortUsb30Enable[1],
+ new->PortUsb30Enable[1]);
+ soc_display_upd_value("PortUsb30Enable[2]", 1, old->PortUsb30Enable[2],
+ new->PortUsb30Enable[2]);
+ soc_display_upd_value("PortUsb30Enable[3]", 1, old->PortUsb30Enable[3],
+ new->PortUsb30Enable[3]);
+ soc_display_upd_value("PortUsb30Enable[4]", 1, old->PortUsb30Enable[4],
+ new->PortUsb30Enable[4]);
+ soc_display_upd_value("PortUsb30Enable[5]", 1, old->PortUsb30Enable[5],
+ new->PortUsb30Enable[5]);
+ soc_display_upd_value("PortUsb30Enable[6]", 1, old->PortUsb30Enable[6],
+ new->PortUsb30Enable[6]);
+ soc_display_upd_value("PortUsb30Enable[7]", 1, old->PortUsb30Enable[7],
+ new->PortUsb30Enable[7]);
+ soc_display_upd_value("PortUsb30Enable[8]", 1, old->PortUsb30Enable[8],
+ new->PortUsb30Enable[8]);
+ soc_display_upd_value("PortUsb30Enable[9]", 1, old->PortUsb30Enable[9],
+ new->PortUsb30Enable[9]);
+ soc_display_upd_value("XdciEnable", 1, old->XdciEnable,
+ new->XdciEnable);
+ soc_display_upd_value("SsicPortEnable", 1, old->SsicPortEnable,
+ new->SsicPortEnable);
+ soc_display_upd_value("SmbusEnable", 1, old->SmbusEnable,
+ new->SmbusEnable);
+ soc_display_upd_value("SerialIoDevMode[0]", 1, old->SerialIoDevMode[0],
+ new->SerialIoDevMode[0]);
+ soc_display_upd_value("SerialIoDevMode[1]", 1, old->SerialIoDevMode[1],
+ new->SerialIoDevMode[1]);
+ soc_display_upd_value("SerialIoDevMode[2]", 1, old->SerialIoDevMode[2],
+ new->SerialIoDevMode[2]);
+ soc_display_upd_value("SerialIoDevMode[3]", 1, old->SerialIoDevMode[3],
+ new->SerialIoDevMode[3]);
+ soc_display_upd_value("SerialIoDevMode[4]", 1, old->SerialIoDevMode[4],
+ new->SerialIoDevMode[4]);
+ soc_display_upd_value("SerialIoDevMode[5]", 1, old->SerialIoDevMode[5],
+ new->SerialIoDevMode[5]);
+ soc_display_upd_value("SerialIoDevMode[6]", 1, old->SerialIoDevMode[6],
+ new->SerialIoDevMode[6]);
+ soc_display_upd_value("SerialIoDevMode[7]", 1, old->SerialIoDevMode[7],
+ new->SerialIoDevMode[7]);
+ soc_display_upd_value("SerialIoDevMode[8]", 1, old->SerialIoDevMode[8],
+ new->SerialIoDevMode[8]);
+ soc_display_upd_value("SerialIoDevMode[9]", 1, old->SerialIoDevMode[9],
+ new->SerialIoDevMode[9]);
+ soc_display_upd_value("SerialIoDevMode[10]", 1,
+ old->SerialIoDevMode[10],
+ new->SerialIoDevMode[10]);
+ soc_display_upd_value("Cio2Enable", 1, old->Cio2Enable,
+ new->Cio2Enable);
+ soc_display_upd_value("ScsEmmcEnabled", 1, old->ScsEmmcEnabled,
+ new->ScsEmmcEnabled);
+ soc_display_upd_value("ScsEmmcHs400Enabled", 1,
+ old->ScsEmmcHs400Enabled,
+ new->ScsEmmcHs400Enabled);
+ soc_display_upd_value("ScsSdCardEnabled", 1, old->ScsSdCardEnabled,
+ new->ScsSdCardEnabled);
+ soc_display_upd_value("IshEnable", 1, old->IshEnable, new->IshEnable);
+ soc_display_upd_value("ShowSpiController", 1, old->ShowSpiController,
+ new->ShowSpiController);
+ soc_display_upd_value("PttSwitch", 1, old->PttSwitch, new->PttSwitch);
+ soc_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts,
+ new->HeciTimeouts);
+ soc_display_upd_value("HsioMessaging", 1, old->HsioMessaging,
+ new->HsioMessaging);
+ soc_display_upd_value("Heci3Enabled", 1, old->Heci3Enabled,
+ new->Heci3Enabled);
+ soc_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc,
+ new->IgdDvmt50PreAlloc);
+ soc_display_upd_value("PrimaryDisplay", 1, old->PrimaryDisplay,
+ new->PrimaryDisplay);
+ soc_display_upd_value("InternalGfx", 1, old->InternalGfx,
+ new->InternalGfx);
+ soc_display_upd_value("ApertureSize", 1, old->ApertureSize,
+ new->ApertureSize);
+ soc_display_upd_value("SkipExtGfxScan", 1, old->SkipExtGfxScan,
+ new->SkipExtGfxScan);
+ soc_display_upd_value("ScanExtGfxForLegacyOpRom", 1,
+ old->ScanExtGfxForLegacyOpRom,
+ new->ScanExtGfxForLegacyOpRom);
+}
diff --git a/src/soc/intel/skylake/romstage/smbus.c b/src/soc/intel/skylake/romstage/smbus.c
index f09459b..b72255f 100644
--- a/src/soc/intel/skylake/romstage/smbus.c
+++ b/src/soc/intel/skylake/romstage/smbus.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,7 +16,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <arch/io.h>
diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c
index a2c5d33..206350b 100644
--- a/src/soc/intel/skylake/romstage/spi.c
+++ b/src/soc/intel/skylake/romstage/spi.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,16 +15,13 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci_ids.h>
-#include <device/pci_def.h>
#include <delay.h>
#include <soc/spi.h>
-#include <soc/rcba.h>
#include <soc/romstage.h>
#define SPI_DELAY 10 /* 10us */
@@ -31,43 +29,47 @@
static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
{
- u32 *ptr32 = (u32*)buffer;
+ u32 *ptr32 = (u32 *)buffer;
u32 i;
+ u16 hsfs, hsfc;
+ void *spibar = get_spi_bar();
/* Clear status bits */
- SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR |
- SPIBAR_HSFS_FDONE;
+ hsfs = read16(spibar + SPIBAR_HSFS);
+ write16(spibar + SPIBAR_HSFS, hsfs | SPIBAR_HSFS_AEL |
+ SPIBAR_HSFS_FCERR | SPIBAR_HSFS_FDONE);
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
+ if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
printk(BIOS_ERR, "SPI ERROR: transaction in progress\n");
return -1;
}
/* Set flash address */
- SPIBAR32(SPIBAR_FADDR) = offset;
+ write32(spibar + SPIBAR_FADDR, offset);
/* Setup read transaction */
- SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) |
- SPIBAR_HSFC_CYCLE_READ;
+ write16(spibar + SPIBAR_HSFC, SPIBAR_HSFC_BYTE_COUNT(size) |
+ SPIBAR_HSFC_CYCLE_READ);
- /* Start transaction */
- SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO;
+ /* Start transactinon */
+ hsfc = read16(spibar + SPIBAR_HSFC);
+ write16(spibar + SPIBAR_HSFC, hsfc | SPIBAR_HSFC_GO);
/* Wait for completion */
for (i = 0; i < SPI_RETRY; i++) {
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
+ if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) {
/* Cycle in progress, wait 1ms */
udelay(SPI_DELAY);
continue;
}
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
+ if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_AEL) {
printk(BIOS_ERR, "SPI ERROR: Access Error\n");
return -1;
}
- if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
+ if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) {
printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n");
return -1;
}
@@ -80,14 +82,18 @@
}
/* Read the data */
- for (i = 0; i < size; i+=sizeof(u32)) {
+ for (i = 0; i < size; i += sizeof(u32)) {
if (size-i >= 4) {
/* reading >= dword */
- *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
+ *ptr32++ = read32(spibar +
+ SPIBAR_FDATA(i/sizeof(u32)));
} else {
/* reading < dword */
- u8 j, *ptr8 = (u8*)ptr32;
- u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
+ u8 j, *ptr8 = (u8 *)ptr32;
+ u32 temp;
+
+ temp = read32(spibar +
+ SPIBAR_FDATA(i/sizeof(u32)));
for (j = 0; j < (size-i); j++) {
*ptr8++ = temp & 0xff;
temp >>= 8;
@@ -122,18 +128,19 @@
int early_spi_read_wpsr(u8 *sr)
{
int retry;
+ void *spibar = get_spi_bar();
/* No address associated with rdsr */
- SPIBAR8(SPIBAR_OPTYPE) = 0x0;
+ write8(spibar + SPIBAR_OPTYPE, 0x0);
/* Setup opcode[0] = read wpsr */
- SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5;
+ write8(spibar + SPIBAR_OPMENU_LOWER, 0x5);
/* Start transaction */
- SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO;
+ write16(spibar + SPIBAR_SSFC, SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO);
/* Wait for error / complete status */
for (retry = SPI_RETRY; retry; retry--) {
- u16 status = SPIBAR16(SPIBAR_SSFS);
+ u16 status = read16(spibar + SPIBAR_SSFS);
if (status & SPIBAR_SSFS_ERROR) {
printk(BIOS_ERR, "SPI rdsr failed\n");
return -1;
@@ -143,7 +150,9 @@
udelay(SPI_DELAY);
}
-
- *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff;
+ /* Flash protected range 0 register bit 31 indicates WP
+ * Bit 31[WPE] 1= WP Enable 0= WP Disable
+ */
+ *sr = (read32(spibar + SPIBAR_FPR(0)) & SPIBAR_FPR_WPE) >> 24;
return 0;
}
diff --git a/src/soc/intel/skylake/romstage/stack.c b/src/soc/intel/skylake/romstage/stack.c
deleted file mode 100644
index a81eb076..0000000
--- a/src/soc/intel/skylake/romstage/stack.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <arch/cpu.h>
-#include <arch/early_variables.h>
-#include <console/console.h>
-#include <cbmem.h>
-#include <cpu/x86/mtrr.h>
-#include <soc/romstage.h>
-
-static inline uint32_t *stack_push(u32 *stack, u32 value)
-{
- stack = &stack[-1];
- *stack = value;
- return stack;
-}
-
-/* Romstage needs quite a bit of stack for decompressing images since the lzma
- * lib keeps its state on the stack during romstage. */
-static unsigned long choose_top_of_stack(void)
-{
- unsigned long stack_top;
- const unsigned long romstage_ram_stack_size = 0x5000;
-
- /* cbmem_add() does a find() before add(). */
- stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
- romstage_ram_stack_size);
- stack_top += romstage_ram_stack_size;
- return stack_top;
-}
-
-/* setup_stack_and_mttrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mttrs(void)
-{
- unsigned long top_of_stack;
- int num_mtrrs;
- uint32_t *slot;
- uint32_t mtrr_mask_upper;
- uint32_t top_of_ram;
-
- /* Top of stack needs to be aligned to a 4-byte boundary. */
- top_of_stack = choose_top_of_stack() & ~3;
- slot = (void *)top_of_stack;
- num_mtrrs = 0;
-
- /* The upper bits of the MTRR mask need to set according to the number
- * of physical address bits. */
- mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
-
- /* The order for each MTTR is value then base with upper 32-bits of
- * each value coming before the lower 32-bits. The reasoning for
- * this ordering is to create a stack layout like the following:
- * +0: Number of MTRRs
- * +4: MTTR base 0 31:0
- * +8: MTTR base 0 63:32
- * +12: MTTR mask 0 31:0
- * +16: MTTR mask 0 63:32
- * +20: MTTR base 1 31:0
- * +24: MTTR base 1 63:32
- * +28: MTTR mask 1 31:0
- * +32: MTTR mask 1 63:32
- */
-
- /* Cache the ROM as WP just below 4GiB. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
- num_mtrrs++;
-
- /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- top_of_ram = (uint32_t)cbmem_top();
- /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the
- * start of the TSEG region. It is required to be 8MiB aligned. Set
- * this area as cacheable so it can be used later for ramstage before
- * setting up the entire RAM as cacheable. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /* Cache 8MiB at the top of ram. Top of ram is where the TSEG
- * region resides. However, it is not restricted to SMM mode until
- * SMM has been relocated. By setting the region to cacheable it
- * provides faster access when relocating the SMM handler as well
- * as using the TSEG region for other purposes. */
- slot = stack_push(slot, mtrr_mask_upper); /* upper mask */
- slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid);
- slot = stack_push(slot, 0); /* upper base */
- slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK);
- num_mtrrs++;
-
- /* Save the number of MTTRs to setup. Return the stack location
- * pointing to the number of MTRRs. */
- slot = stack_push(slot, num_mtrrs);
-
- return slot;
-}
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 7a43917..36f6871 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -3,6 +3,7 @@
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,7 +16,7 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
#include <stdlib.h>
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
index 96c9634..8ddcbad 100644
--- a/src/soc/intel/skylake/romstage/uart.c
+++ b/src/soc/intel/skylake/romstage/uart.c
@@ -1,7 +1,8 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2015 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,72 +15,61 @@
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Foundation, Inc.
*/
-#include <arch/early_variables.h>
#include <arch/io.h>
-#include <delay.h>
#include <device/pci_def.h>
-#include <reg_script.h>
#include <stdint.h>
-#include <uart8250.h>
-#include <soc/iobp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr.h>
+#include <soc/romstage.h>
#include <soc/serialio.h>
-const struct reg_script uart_init[] = {
- /* Set MMIO BAR */
- REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
- /* Enable Memory access and Bus Master */
- REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER),
- /* Initialize LTR */
- REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN,
- ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0),
- REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
- ~(SIO_REG_PPR_RST_ASSERT), 0),
- /* Take UART out of reset */
- REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST,
- SIO_REG_PPR_RST_ASSERT),
- /* Set M and N divisor inputs and enable clock */
- REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK,
- SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
- (SIO_REG_PPR_CLOCK_N_DIV << 16) |
- (SIO_REG_PPR_CLOCK_M_DIV << 1)),
- REG_SCRIPT_END
-};
-
void pch_uart_init(void)
{
- /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */
- u32 gpiodf = 0x131f;
device_t dev;
+ u32 tmp, legacy;
+ u8 *base = (u8 *)CONFIG_TTYS0_BASE;
- /* Put UART in byte access mode for 16550 compatibility */
switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
case 0:
dev = PCH_DEV_UART0;
- gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS;
+ legacy = SIO_PCH_LEGACY_UART0;
break;
case 1:
dev = PCH_DEV_UART1;
- gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS;
+ legacy = SIO_PCH_LEGACY_UART1;
+ break;
+ case 2:
+ dev = PCH_DEV_UART2;
+ legacy = SIO_PCH_LEGACY_UART2;
break;
default:
return;
}
- /* Program IOBP GPIODF */
- pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf);
+ /* Set configured UART base address */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
- /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */
- pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
+ /* Enable memory access and bus master */
+ tmp = pci_read_config32(dev, PCI_COMMAND);
+ tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, tmp);
- /* Initialize chipset uart interface */
- reg_script_run_on_dev(dev, uart_init);
+ /* Take UART out of reset */
+ tmp = read32(base + SIO_REG_PPR_RESETS);
+ tmp |= SIO_REG_PPR_RESETS_FUNC | SIO_REG_PPR_RESETS_APB |
+ SIO_REG_PPR_RESETS_IDMA;
+ write32(base + SIO_REG_PPR_RESETS, tmp);
- /*
- * Perform standard UART initialization
- * Divisor 1 is 115200 BAUD
- */
- uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
+ /* Set M and N divisor inputs and enable clock */
+ tmp = read32(base + SIO_REG_PPR_CLOCK);
+ tmp |= SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE |
+ (SIO_REG_PPR_CLOCK_N_DIV << 16) |
+ (SIO_REG_PPR_CLOCK_M_DIV << 1);
+ write32(base + SIO_REG_PPR_CLOCK, tmp);
+
+ /* Put UART in byte access mode for 16550 compatibility */
+ pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, legacy);
}