tree 030bc6154a841b5ca66e48e52b9ad667c8edb151
parent 6dba745cc8627b0a316141f16a6662890e2cb419
author Matt DeVillier <matt.devillier@gmail.com> 1697765468 -0500
committer Felix Singer <service+coreboot-gerrit@felixsinger.de> 1698764608 +0000

soc/intel/tigerlake: Implement SoC sleep state array

Copied from Alderlake implementation, modified as needed for Tigerlake.
Device names missing from soc_acpi_name() were added as well.

TEST=build/boot Win11, Linux on google/volteer (drobit).

Change-Id: I34999891ea0d386328698109b6315d481de7c43a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78521
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>