commit 1c920108499a7394bd072a7be380e491eac6fa28
author Rex-BC Chen <rex-bc.chen@mediatek.com> Tue May 04 10:32:54 2021 +0800
committer Hung-Te Lin <hungte@chromium.org> Wed May 05 07:37:05 2021 +0000
tree c1f48b0ce4c6502fe6346069e146b0ae7b0b2747
parent f46e2caebec91d83bd729e6812e51ca960a24f38

soc/mediatek/mt8195: Add NOR-Flash support

TEST=boot to romstage on MT8195 EVB

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I450281fb4b1750e59cb76f6b2083f0e2889fd4cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8195/Kconfig

diff --git a/src/soc/mediatek/mt8195/Kconfig b/src/soc/mediatek/mt8195/Kconfig
index 76329cd..bed3e04 100644
--- a/src/soc/mediatek/mt8195/Kconfig
+++ b/src/soc/mediatek/mt8195/Kconfig
@@ -17,4 +17,11 @@
 	select VBOOT_SEPARATE_VERSTAGE
 	select VBOOT_RETURN_FROM_VERSTAGE
 
+config FLASH_DUAL_READ
+	bool
+	default y
+	help
+	  When this option is enabled, the flash controller provides the ability
+	  to dual read mode.
+
 endif

src/soc/mediatek/mt8195/Makefile.inc

diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index 04f4572..0c5b9cf 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -1,6 +1,7 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y)
 
 bootblock-y += bootblock.c
+bootblock-y += ../common/flash_controller.c
 bootblock-y += ../common/gpio.c gpio.c
 bootblock-y += ../common/mmu_operations.c
 bootblock-y += ../common/pll.c pll.c
@@ -9,6 +10,7 @@
 bootblock-y += ../common/uart.c
 bootblock-y += ../common/wdt.c
 
+verstage-y += ../common/flash_controller.c
 verstage-y += ../common/gpio.c gpio.c
 verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 verstage-y += ../common/timer.c timer.c
@@ -17,6 +19,7 @@
 
 romstage-y += ../common/cbmem.c
 romstage-y += emi.c
+romstage-y += ../common/flash_controller.c
 romstage-y += ../common/gpio.c gpio.c
 romstage-y += ../common/pll.c pll.c
 romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
@@ -30,6 +33,7 @@
 romstage-y += ../common/mt6359p.c mt6359p.c
 
 ramstage-y += emi.c
+ramstage-y += ../common/flash_controller.c
 ramstage-y += ../common/gpio.c gpio.c
 ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 ramstage-y += soc.c

src/soc/mediatek/mt8195/include/soc/symbols.h

diff --git a/src/soc/mediatek/mt8195/include/soc/symbols.h b/src/soc/mediatek/mt8195/include/soc/symbols.h
new file mode 100644
index 0000000..76d9c6d
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/symbols.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_MEDIATEK_MT8195_SYMBOLS_H_
+#define _SOC_MEDIATEK_MT8195_SYMBOLS_H_
+#include <symbols.h>
+
+DECLARE_REGION(dram_dma)
+
+#endif /* _SOC_MEDIATEK_MT8195_SYMBOLS_H_ */

src/soc/mediatek/mt8195/spi.c

diff --git a/src/soc/mediatek/mt8195/spi.c b/src/soc/mediatek/mt8195/spi.c
index bc02aa0..cfa52c4 100644
--- a/src/soc/mediatek/mt8195/spi.c
+++ b/src/soc/mediatek/mt8195/spi.c
@@ -3,6 +3,7 @@
 #include <assert.h>
 #include <device/mmio.h>
 #include <soc/addressmap.h>
+#include <soc/flash_controller_common.h>
 #include <soc/gpio.h>
 #include <soc/spi.h>
 
@@ -93,6 +94,7 @@
 
 static const struct spi_ctrlr spi_flash_ctrlr = {
 	.max_xfer_size = 65535,
+	.flash_probe = mtk_spi_flash_probe,
 };
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
@@ -103,6 +105,8 @@
 	},
 	{
 		.ctrlr = &spi_flash_ctrlr,
+		.bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
+		.bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
 	},
 };