diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index a5b2e5e..6380681 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -22,6 +22,7 @@
 romstage-y += early_dmi.c
 romstage-y += raminit.c
 romstage-y += raminit_common.c
+romstage-y += raminit_iosav.c
 romstage-y += raminit_native.c
 romstage-y += raminit_tables.c
 romstage-y += ../../../device/dram/ddr3.c
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 20c048f..ebb9e44 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -18,31 +18,6 @@
 
 /* FIXME: no support for 3-channel chipsets */
 
-/* Number of programmed IOSAV subsequences. */
-static unsigned int ssq_count = 0;
-
-static void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq)
-{
-	MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw;
-	MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw;
-	MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw;
-	MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw;
-
-	ssq_count++;
-}
-
-static void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer)
-{
-	MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22);
-
-	ssq_count = 0;
-}
-
-static void iosav_run_once(const int ch)
-{
-	iosav_run_queue(ch, 1, 0);
-}
-
 static void sfence(void)
 {
 	asm volatile ("sfence");
@@ -546,14 +521,6 @@
 	}
 }
 
-static void wait_for_iosav(int channel)
-{
-	while (1) {
-		if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50)
-			return;
-	}
-}
-
 static void write_reset(ramctr_timing *ctrl)
 {
 	int channel, slotrank;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index a6f4e0b..73c28bc 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -98,6 +98,11 @@
 	} addr_update;
 };
 
+void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq);
+void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer);
+void iosav_run_once(const int ch);
+void wait_for_iosav(int channel);
+
 /* FIXME: Vendor BIOS uses 64 but our algorithms are less
    performant and even 1 seems to be enough in practice.  */
 #define NUM_PATTERNS	4
diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c
new file mode 100644
index 0000000..9ab415a
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/raminit_iosav.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <commonlib/helpers.h>
+#include <console/console.h>
+#include <delay.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "raminit_common.h"
+#include "raminit_tables.h"
+#include "sandybridge.h"
+
+/* FIXME: no support for 3-channel chipsets */
+
+/* Number of programmed IOSAV subsequences. */
+static unsigned int ssq_count = 0;
+
+void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq)
+{
+	MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(ch, ssq_count)) = ssq->sp_cmd_ctrl.raw;
+	MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(ch, ssq_count)) = ssq->subseq_ctrl.raw;
+	MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(ch, ssq_count)) = ssq->sp_cmd_addr.raw;
+	MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(ch, ssq_count)) = ssq->addr_update.raw;
+
+	ssq_count++;
+}
+
+void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer)
+{
+	MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22);
+
+	ssq_count = 0;
+}
+
+void iosav_run_once(const int ch)
+{
+	iosav_run_queue(ch, 1, 0);
+}
+
+void wait_for_iosav(int channel)
+{
+	while (1) {
+		if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50)
+			return;
+	}
+}