diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 6501bc4..952cc7b 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -98,4 +98,12 @@
 config INTEL_GMA_BCLV_OFFSET
 	default 0x48254
 
+config ENABLE_DDR_2X_REFRESH
+	bool "Enable DRAM Refresh 2x support"
+	default n
+	help
+	  When enabled, the memory controller will refresh the DRAM twice as often.
+	  This probably only happens when the DRAM gets hot, but what MRC exactly
+	  does when this setting is enabled has not been investigated.
+
 endif
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index ca94813..42a2a56 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -52,6 +52,7 @@
 		.gpiobase = DEFAULT_GPIOBASE,
 		.temp_mmio_base = 0xfed08000,
 		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH),
 		.max_ddr3_freq = 1600,
 	};