nb/intel/gm45: Define and use MMCONF_BUS_NUMBER
Change-Id: I635f3615f566502f79bbd81f9f743ce63bba3b1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49758
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 4637a22..256b088 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,6 +29,10 @@
config MMCONF_BASE_ADDRESS
default 0xf0000000
+config MMCONF_BUS_NUMBER
+ int
+ default 64
+
config SMM_RESERVED_SIZE
hex
default 0x100000
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index 4a8696d..d88fdb7 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -13,15 +13,8 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
- u32 length, pciexbar;
-
- if (!decode_pcie_bar(&pciexbar, &length))
- return current;
-
- const int max_buses = length / MiB;
-
- current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
- pciexbar, 0x0, 0x0, max_buses - 1);
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
+ CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
return current;
}
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index f13133d..7f64219 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -18,7 +18,7 @@
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
- Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
+ Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index 2e41981..9c45f7e 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,14 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
+#include <assert.h>
#include <device/pci_ops.h>
+#include <types.h>
#include "gm45.h"
+static uint32_t encode_pciexbar_length(void)
+{
+ switch (CONFIG_MMCONF_BUS_NUMBER) {
+ case 256: return 0 << 1;
+ case 128: return 1 << 1;
+ case 64: return 2 << 1;
+ default: return dead_code_t(uint32_t);
+ }
+}
+
void bootblock_early_northbridge_init(void)
{
- uint32_t reg;
-
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
@@ -21,8 +31,7 @@
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
- reg = 0;
- pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg);
- reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */
- pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
+ const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+ pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
+ pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg);
}
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 6854b73..ae8b839 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -444,8 +444,6 @@
int get_blc_values(const struct blc_pwm_t **entries);
u16 get_blc_pwm_freq_value(const char *edid_ascii_string);
-int decode_pcie_bar(u32 *const base, u32 *const len);
-
#include <device/device.h>
struct acpi_rsdp;
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 3458cbf..561c2fc 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -14,43 +14,10 @@
#include "chip.h"
#include "gm45.h"
-int decode_pcie_bar(u32 *const base, u32 *const len)
-{
- *base = 0;
- *len = 0;
-
- struct device *dev = pcidev_on_root(0, 0);
- if (!dev)
- return 0;
-
- const u32 pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
-
- if (!(pciexbar_reg & (1 << 0)))
- return 0;
-
- switch ((pciexbar_reg >> 1) & 3) {
- case 0: /* 256MB */
- *base = pciexbar_reg & (0x0f << 28);
- *len = 256 * MiB;
- return 1;
- case 1: /* 128M */
- *base = pciexbar_reg & (0x1f << 27);
- *len = 128 * MiB;
- return 1;
- case 2: /* 64M */
- *base = pciexbar_reg & (0x3f << 26);
- *len = 64 * MiB;
- return 1;
- }
-
- return 0;
-}
-
static void mch_domain_read_resources(struct device *dev)
{
u64 tom, touud;
u32 tomk, tolud, uma_sizek = 0, delta_cbmem;
- u32 pcie_config_base, pcie_config_size;
/* Total Memory 2GB example:
*
@@ -157,12 +124,7 @@
/* Don't use uma_resource() as our UMA touches the PCI hole. */
fixed_mem_resource(dev, 8, tomk, uma_sizek, IORESOURCE_RESERVE);
- if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
- printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
- "size=0x%x\n", pcie_config_base, pcie_config_size);
- fixed_mem_resource(dev, 9, pcie_config_base >> 10,
- pcie_config_size >> 10, IORESOURCE_RESERVE);
- }
+ mmconf_resource(dev, 9);
}
static void mch_domain_set_resources(struct device *dev)