Initial Intel 440BX RAM initialization framework.
This does _not_ fully work, yet. You will _not_ be able to boot any
payload with this code, yet.
Add missing license headers.
Base the northbridge.c file on the Intel 855PM version, that comes
closer to what we want.
The raminit.c file is written from scratch and hardcodes several
values for now. This needs to be fixed later by reading the
correct values via SPD.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index 6e40683..3612f31 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -1,11 +1,33 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#ifndef RAMINIT_H
#define RAMINIT_H
+/* The 440BX supports up to four (single- or double-sided) DIMMs. */
#define DIMM_SOCKETS 4
+
+/* The 440BX memory controller has one channel only. */
struct mem_controller {
- device_t d0;
- uint16_t channel0[DIMM_SOCKETS];
+ device_t d0;
+ uint16_t channel0[DIMM_SOCKETS];
};
-
-#endif /* RAMINIT_H */
+#endif /* RAMINIT_H */