tree 2355cc04a346d505bda93f8fa316e79cde858e38
parent a94a153477584ba2d168021f23fa571f048e6767
author Mario Scheithauer <mario.scheithauer@siemens.com> 1543393318 +0100
committer Patrick Georgi <pgeorgi@google.com> 1543493852 +0000

siemens/mc_apl5: Disable PCI clock outputs on XIO bridges

On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.

Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29882
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>