device/smbus_host: Declare common early SMBus prototypes
Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h
index cae4f3f..5782d5e 100644
--- a/src/include/device/smbus.h
+++ b/src/include/device/smbus.h
@@ -29,6 +29,7 @@
struct bus *get_pbus_smbus(struct device *dev);
+#if !DEVTREE_EARLY
static inline int smbus_recv_byte(struct device *const dev)
{
return i2c_dev_readb(dev);
@@ -51,5 +52,6 @@
int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer);
int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer);
+#endif
#endif /* DEVICE_SMBUS_H */
diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h
index d9390ea..4bc8009 100644
--- a/src/include/device/smbus_host.h
+++ b/src/include/device/smbus_host.h
@@ -41,4 +41,42 @@
printk(BIOS_DEBUG, "SMBus controller enabled\n");
}
+#if DEVTREE_EARLY
+static inline int smbus_read_byte(u8 device, u8 address)
+{
+ uintptr_t base = smbus_base();
+ return do_smbus_read_byte(base, device, address);
+}
+
+static inline int smbus_read_word(u8 device, u8 address)
+{
+ uintptr_t base = smbus_base();
+ return do_smbus_read_word(base, device, address);
+}
+
+static inline int smbus_write_byte(u8 device, u8 address, u8 data)
+{
+ uintptr_t base = smbus_base();
+ return do_smbus_write_byte(base, device, address, data);
+}
+
+static inline int smbus_block_read(u8 device, u8 cmd, size_t max_bytes, u8 *buf)
+{
+ uintptr_t base = smbus_base();
+ return do_smbus_block_read(base, device, cmd, max_bytes, buf);
+}
+
+static inline int smbus_block_write(u8 device, u8 cmd, size_t bytes, const u8 *buf)
+{
+ uintptr_t base = smbus_base();
+ return do_smbus_block_write(base, device, cmd, bytes, buf);
+}
+
+static inline int i2c_eeprom_read(u8 device, u8 offset, size_t bytes, u8 *buf)
+{
+ uintptr_t base = smbus_base();
+ return do_i2c_eeprom_read(base, device, offset, bytes, buf);
+}
+#endif
+
#endif
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index d60bd5b..05a4cf2 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -3,8 +3,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <ec/acpi/ec.h>
-
-#include <southbridge/intel/ibexpeak/pch.h>
+#include <device/smbus_host.h>
#include <northbridge/intel/ironlake/ironlake.h>
const struct southbridge_usb_port mainboard_usb_ports[] = {
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index b87ba6e..404ab2f 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <lib.h>
#include <commonlib/helpers.h>
#include <console/console.h>
@@ -24,7 +25,6 @@
#include <spd.h>
#include <sdram_mode.h>
#include <timestamp.h>
-#include <southbridge/intel/i82801dx/i82801dx.h>
#include "raminit.h"
#include "e7505.h"
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index fbf9f01..86c7ace 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -7,6 +7,7 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/device.h>
+#include <device/smbus_host.h>
#include <spd.h>
#include <console/console.h>
#include <lib.h>
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index b2b9617..63b8e8f 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -2,8 +2,8 @@
#include <console/console.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <spd.h>
-#include <southbridge/intel/i82371eb/i82371eb.h>
#include "raminit.h"
void dump_spd_registers(void)
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 1910813..e5d377e 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -6,13 +6,12 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
+#include <device/smbus_host.h>
#include <console/console.h>
#include <timestamp.h>
#include "i440bx.h"
#include "raminit.h"
-#include <southbridge/intel/i82371eb/i82371eb.h>
-
/*
* Macros and definitions
*/
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 65da1ae..db987ca 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -3,6 +3,7 @@
#include <spd.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
+#include <device/smbus_host.h>
#include <console/console.h>
#include "i945.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c668e79..1c7a1f0 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -4,6 +4,7 @@
#include <delay.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <cf9_reset.h>
#include <device/mmio.h>
#include <device/device.h>
diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index e85163f..13f0c35 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -6,6 +6,7 @@
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include <cbmem.h>
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index af846e3..43149be 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -3,6 +3,7 @@
#include <cf9_reset.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <delay.h>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 72c284f..422067b 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -89,10 +89,10 @@
int j;
if (id_only) {
for (j = 117; j < 128; j++)
- (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j);
+ (*spd)[j] = smbus_read_byte(addr, j);
} else {
for (j = 0; j < 256; j++)
- (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j);
+ (*spd)[j] = smbus_read_byte(addr, j);
}
}
diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c
index 5fc9a7a..174e8b5 100644
--- a/src/northbridge/intel/x4x/raminit.c
+++ b/src/northbridge/intel/x4x/raminit.c
@@ -1,15 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/pci_ops.h>
+#include <device/smbus_host.h>
#include <cbmem.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <arch/cpu.h>
-#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
-#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */
-#else
-#include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */
-#endif
#include <spd.h>
#include <string.h>
#include <device/dram/ddr2.h>
diff --git a/src/soc/intel/common/block/smbus/Makefile.inc b/src/soc/intel/common/block/smbus/Makefile.inc
index 309ad9a..53dc15e 100644
--- a/src/soc/intel/common/block/smbus/Makefile.inc
+++ b/src/soc/intel/common/block/smbus/Makefile.inc
@@ -6,7 +6,6 @@
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus_early.c
romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
-ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbuslib.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c
diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c
index 85a16b3..cc59c28 100644
--- a/src/soc/intel/common/block/smbus/smbus_early.c
+++ b/src/soc/intel/common/block/smbus/smbus_early.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/pci_def.h>
+#include <device/smbus_host.h>
#include <intelblocks/smbus.h>
#include <reg_script.h>
#include <soc/pci_devs.h>
@@ -25,3 +26,8 @@
{
reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script);
}
+
+uintptr_t smbus_base(void)
+{
+ return SMBUS_IO_BASE;
+}
diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c
index 8f337c1..17b6377 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.c
+++ b/src/soc/intel/common/block/smbus/smbuslib.c
@@ -31,9 +31,9 @@
for (i = 0; i < SPD_PAGE_LEN; i += step) {
if (CONFIG(SPD_READ_BY_WORD))
((u16*)spd)[i / sizeof(uint16_t)] =
- do_smbus_read_word(SMBUS_IO_BASE, addr, i);
+ smbus_read_word(addr, i);
else
- spd[i] = do_smbus_read_byte(SMBUS_IO_BASE, addr, i);
+ spd[i] = smbus_read_byte(addr, i);
}
}
@@ -41,30 +41,28 @@
static int get_spd(u8 *spd, u8 addr)
{
/* If address is not 0, it will return CB_ERR(-1) if no dimm */
- if (do_smbus_read_byte(SMBUS_IO_BASE, addr, 0) < 0) {
+ if (smbus_read_byte(addr, 0) < 0) {
printk(BIOS_INFO, "No memory dimm at address %02X\n",
addr << 1);
return -1;
}
- if (do_i2c_eeprom_read(SMBUS_IO_BASE, addr, 0, SPD_PAGE_LEN, spd) == SMBUS_ERROR) {
+ if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) {
printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
smbus_read_spd(spd, addr);
}
/* Check if module is DDR4, DDR4 spd is 512 byte. */
- if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
- CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
+ if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
/* Switch to page 1 */
- do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_1, 0, 0);
+ smbus_write_byte(SPD_PAGE_1, 0, 0);
- if (do_i2c_eeprom_read(SMBUS_IO_BASE, addr, 0, SPD_PAGE_LEN,
- spd + SPD_PAGE_LEN) == SMBUS_ERROR) {
+ if (i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) {
printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n");
smbus_read_spd(spd + SPD_PAGE_LEN, addr);
}
/* Restore to page 0 */
- do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0);
+ smbus_write_byte(SPD_PAGE_0, 0, 0);
}
return 0;
}
@@ -105,7 +103,7 @@
return CB_ERR;
/* If dimm is not present, set sn to 0xff. */
- smbus_ret = do_smbus_read_byte(SMBUS_IO_BASE, addr, SPD_DRAM_TYPE);
+ smbus_ret = smbus_read_byte(addr, SPD_DRAM_TYPE);
if (smbus_ret < 0) {
printk(BIOS_INFO, "No memory dimm at address %02X\n", addr);
*sn = 0xffffffff;
@@ -117,17 +115,17 @@
/* Check if module is DDR4, DDR4 spd is 512 byte. */
if (dram_type == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) {
/* Switch to page 1 */
- do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_1, 0, 0);
+ smbus_write_byte(SPD_PAGE_1, 0, 0);
for (i = 0; i < SPD_SN_LEN; i++)
- *((u8 *)sn + i) = do_smbus_read_byte(SMBUS_IO_BASE, addr,
+ *((u8 *)sn + i) = smbus_read_byte(addr,
i + DDR4_SPD_SN_OFF);
/* Restore to page 0 */
- do_smbus_write_byte(SMBUS_IO_BASE, SPD_PAGE_0, 0, 0);
+ smbus_write_byte(SPD_PAGE_0, 0, 0);
} else if (dram_type == SPD_DRAM_DDR3) {
for (i = 0; i < SPD_SN_LEN; i++)
- *((u8 *)sn + i) = do_smbus_read_byte(SMBUS_IO_BASE, addr,
+ *((u8 *)sn + i) = smbus_read_byte(addr,
i + DDR3_SPD_SN_OFF);
} else {
printk(BIOS_ERR, "Unsupported dram_type\n");
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 3e94c15..7d8503b 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -32,8 +32,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index a8c14c9..ed75505 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -48,10 +48,6 @@
void enable_usb_bar(void);
-#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned int device, unsigned int address);
-#endif
-
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
void southbridge_rcba_config(void);
diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c
index cbafd725..97cf5fd 100644
--- a/src/southbridge/intel/i82371eb/early_smbus.c
+++ b/src/southbridge/intel/i82371eb/early_smbus.c
@@ -44,8 +44,3 @@
return 0;
}
-
-int smbus_read_byte(u8 device, u8 address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index a08be0d..e20cb5f 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -8,10 +8,6 @@
void enable_pm(void);
void i82371eb_early_init(void);
-#if ENV_ROMSTAGE
-int smbus_read_byte(u8 device, u8 address);
-#endif
-
#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 5cf203d..6649c33 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -28,8 +28,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 77e4269..d5f09aa 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -16,11 +16,9 @@
#if !defined(__ASSEMBLER__)
#include <device/device.h>
-#include "chip.h"
void i82801dx_enable(struct device *dev);
void i82801dx_early_init(void);
-int smbus_read_byte(unsigned int device, unsigned int address);
void aseg_smm_lock(void);
#endif
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 4d4ecb1..48d9d58 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -30,23 +30,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf)
-{
- return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf);
-}
-
-int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
-{
- return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
-
-int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
-{
- return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 71510a4..fbb6bf1 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -28,15 +28,7 @@
void i82801gx_setup_bars(void);
void i82801gx_early_init(void);
-#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned int device, unsigned int address);
-int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
- u8 *buf);
-int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
-int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
- const u8 *buf);
void ich7_setup_cir(void);
-#endif
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 556fe1a..ba0b0c8 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -32,8 +32,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 6ff696b..58a49f1 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -198,10 +198,6 @@
void i82801ix_dmi_setup(void);
void i82801ix_dmi_poll_vc1(void);
-#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned int device, unsigned int address);
-#endif
-
#endif
#endif
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 87b7ba5..55b9854 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -27,24 +27,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf)
-{
- return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf);
-}
-
-int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
-{
- return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
-
-int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
- const u8 *buf)
-{
- return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 0c99d20..842e049 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -210,14 +210,6 @@
}
#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
-#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned int device, unsigned int address);
-int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
- u8 *buf);
-int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
-int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
- const u8 *buf);
-#endif
void i82801jx_lpc_setup(void);
void i82801jx_setup_bars(void);
void i82801jx_early_init(void);
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index f340aef..7d8503b 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -32,23 +32,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-int smbus_write_byte(unsigned int device, unsigned int address, u8 data)
-{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
-}
-
-int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
-{
- return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
-
-int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
-{
- return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
-}
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index a40fc64..d0f1314 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -39,13 +39,6 @@
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void enable_usb_bar(void);
-#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned int device, unsigned int address);
-int smbus_write_byte(unsigned int device, unsigned int address, u8 data);
-int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
-int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf);
-#endif
-
void early_pch_init(void);
void early_thermal_init(void);
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index 3e94c15..7d8503b 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -32,8 +32,3 @@
return 0;
}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 19f8637..093ebfa 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -160,11 +160,6 @@
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
-
-#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned int device, unsigned int address);
-#endif
-
void enable_usb_bar(void);
int early_pch_init(const void *gpio_map,
const struct rcba_config_instruction *rcba_config);