diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 75f3b7a..6cd1f6f 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -215,6 +215,19 @@
 	return 0;
 }
 
+uintptr_t gma_get_gnvs_aslb(const void *gnvs)
+{
+	const global_nvs_t *gnvs_ptr = gnvs;
+	return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
+}
+
+void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
+{
+	global_nvs_t *gnvs_ptr = gnvs;
+	if (gnvs_ptr)
+		gnvs_ptr->aslb = aslb;
+}
+
 static void power_well_enable(void)
 {
 	gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
@@ -527,7 +540,7 @@
 	gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
 	if (gnvs) {
 		/* IGD OpRegion Base Address */
-		gnvs->aslb = (u32)(uintptr_t)opregion;
+		gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
 	} else {
 		printk(BIOS_ERR, "Error: GNVS table not found.\n");
 	}