tree 72b9e7701ec7a040a8b42e27d9ee14a8dfcdd083
parent 92d59931c42df35358dbeaa090d511d340cb1431
author Wenbin Mei <wenbin.mei@mediatek.com> 1600999382 +0800
committer Hung-Te Lin <hungte@chromium.org> 1608100032 +0000

soc/mediatek/mt8192: ufs: Disable reference clock

UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>