commit 193203f90b49de06e4997aad53fb6d556c34798f
author Deepti Deshatty <deepti.deshatty@intel.com> Thu Apr 29 21:32:58 2021 +0530
committer Patrick Georgi <pgeorgi@google.com> Mon Jun 14 05:55:30 2021 +0000
tree 354bee59790a12266bbeee14f944369d34cc4b78
parent b035f589401b0060771be432851c339843fffeca

mb/intel/adlrvp: Add board id for MR DDR5 SKU

Add support for Maple Ridge DDR5 SKU with boardid 0x16

TEST=Verified build for ADL-P Chrome RVP
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com>
Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>

src/mainboard/intel/adlrvp/include/baseboard/variants.h

diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index af64148..9a94db2 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -13,7 +13,8 @@
 	ADL_P_LP4_1 = 0x10,
 	ADL_P_LP4_2 = 0x11,
 	/* ADL-P DDR5 RVPs */
-	ADL_P_DDR5 = 0x12,
+	ADL_P_DDR5_1 = 0x12,
+	ADL_P_DDR5_2 = 0x16,
 	/* ADL-P LPDDR5 RVP */
 	ADL_P_LP5_1 = 0x13,
 	ADL_P_LP5_2 = 0x17,

src/mainboard/intel/adlrvp/mainboard.c

diff --git a/src/mainboard/intel/adlrvp/mainboard.c b/src/mainboard/intel/adlrvp/mainboard.c
index 0ab80d2..eb86773 100644
--- a/src/mainboard/intel/adlrvp/mainboard.c
+++ b/src/mainboard/intel/adlrvp/mainboard.c
@@ -47,7 +47,8 @@
 	case ADL_P_LP5_1:
 	case ADL_P_LP5_2:
 		return "vbt_adlrvp_lp5.bin";
-	case ADL_P_DDR5:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
 		return "vbt_adlrvp_ddr5.bin";
 	default:
 		return "vbt.bin";

src/mainboard/intel/adlrvp/memory.c

diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 29eb744..353cf4e 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -300,7 +300,8 @@
 	case ADL_P_DDR4_1:
 	case ADL_P_DDR4_2:
 		return &ddr4_mem_config;
-	case ADL_P_DDR5:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
 		return &ddr5_mem_config;
 	case ADL_P_LP5_1:
 	case ADL_P_LP5_2:

src/mainboard/intel/adlrvp/romstage_fsp_params.c

diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 2c61125..9fff257 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -52,7 +52,8 @@
 	switch (board_id) {
 	case ADL_P_DDR4_1:
 	case ADL_P_DDR4_2:
-	case ADL_P_DDR5:
+	case ADL_P_DDR5_1:
+	case ADL_P_DDR5_2:
 		memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated);
 		break;
 	case ADL_P_LP4_1: