soc/amd/common/include/data_fabric_defs: introduce & use DF_REG_* macros
To have both the PCI function number and the register offset into the
config space of that function of the data fabric device in the data
fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN
and DF_REG_REG macros. The DF_REG_ID macro is used for register
definitions where both the function number and the register offset are
specified, and the DF_REG_FN and DF_REG_REG macros are used to extract
the function number and the register offset from the register defines.
This will allow having one define for accessing an indexed group of
registers that are on different functions of the data fabric device.
TEST=MMIO resources read from the data fabric's MMIO decode registers
don't change on Mandolin and the ACPI CRAT table is also identical.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63a284b26081c170a217b082b100c482f6158e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c
index 1b33f31..f28bb12 100644
--- a/src/soc/amd/common/block/data_fabric/domain.c
+++ b/src/soc/amd/common/block/data_fabric/domain.c
@@ -38,8 +38,8 @@
static void data_fabric_get_mmio_base_size(unsigned int reg,
resource_t *mmio_base, resource_t *mmio_limit)
{
- const uint32_t base_reg = data_fabric_broadcast_read32(0, DF_MMIO_BASE(reg));
- const uint32_t limit_reg = data_fabric_broadcast_read32(0, DF_MMIO_LIMIT(reg));
+ const uint32_t base_reg = data_fabric_broadcast_read32(DF_MMIO_BASE(reg));
+ const uint32_t limit_reg = data_fabric_broadcast_read32(DF_MMIO_LIMIT(reg));
/* The raw register values are bits 47..16 of the actual address */
*mmio_base = (resource_t)base_reg << D18F0_MMIO_SHIFT;
*mmio_limit = (((resource_t)limit_reg + 1) << D18F0_MMIO_SHIFT) - 1;
@@ -101,7 +101,7 @@
(1ULL << get_usable_physical_address_bits()) - DF_RESERVED_TOP_12GB_MMIO_SIZE;
for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
- ctrl.raw = data_fabric_broadcast_read32(0, DF_MMIO_CONTROL(i));
+ ctrl.raw = data_fabric_broadcast_read32(DF_MMIO_CONTROL(i));
/* Relevant MMIO regions need to have both reads and writes enabled */
if (!ctrl.we || !ctrl.re)