x60,t60,x201,macbook21 : Declare GPIs for EC
For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb)
programming to use GPI1 between SCI/SMI modes, while
previous programming was for GPI12.
Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c
index 449e367..f90bb38 100644
--- a/src/mainboard/apple/macbook21/smihandler.c
+++ b/src/mainboard/apple/macbook21/smihandler.c
@@ -27,6 +27,8 @@
#include <pc80/mc146818rtc.h>
#include <delay.h>
+#define GPE_EC_SCI 12
+
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
@@ -69,7 +71,7 @@
switch(data) {
case APM_CNT_ACPI_ENABLE:
/* route H8SCI to SCI */
- outw(inw(pmbase + ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x02;
@@ -77,7 +79,7 @@
break;
case APM_CNT_ACPI_DISABLE:
/* route H8SCI# to SMI */
- outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+ outw(inw(pmbase + ALT_GP_SMI_EN) | (1<<GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
tmp &= ~0x03;
tmp |= 0x01;