diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index d1e16e2..e6704f0 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -122,6 +122,22 @@
 	bool
 	default n
 
+config INTEL_GMA_VERSION_2
+	bool
+	default n
+	help
+	  Intel display port and pipe related register definitions have changed since
+	  Tiger Lake SoC. This option enables support for the updated `TRANS_DDI_FUNC_CTL`
+	  register definitions.
+
+	  SoCs that support Intel GMA Version 2 include:
+	  * Alder Lake
+	  * Meteor Lake
+	  * Tiger Lake
+
+	  If you are unsure whether your SoC supports Intel GMA Version 2, it is safe to
+	  disable this option.
+
 if GFX_GMA || EARLY_GFX_GMA
 
 config GFX_GMA_DYN_CPU
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 8e9fc90..5c34104 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -30,6 +30,12 @@
 	PORT_A = 0,
 	PORT_B,
 	PORT_C,
+#if CONFIG(INTEL_GMA_VERSION_2)
+	PORT_USB_C1,
+	PORT_USB_C2,
+	PORT_USB_C3,
+	PORT_USB_C4,
+#endif
 	PORT_D,
 	PORT_E,
 	I915_NUM_PORTS
@@ -39,6 +45,9 @@
 	PIPE_A = 0,
 	PIPE_B,
 	PIPE_C,
+#if CONFIG(INTEL_GMA_VERSION_2)
+	PIPE_D,
+#endif
 	I915_NUM_PIPES
 };
 
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h
index 8a7ccf7..3d6cd45 100644
--- a/src/drivers/intel/gma/i915_reg.h
+++ b/src/drivers/intel/gma/i915_reg.h
@@ -4181,9 +4181,17 @@
 						   TRANS_DDI_FUNC_CTL_B)
 #define  TRANS_DDI_FUNC_ENABLE		(1UL<<31)
 /* Those bits are ignored by pipe EDP since it can only connect to DDI A */
-#define  TRANS_DDI_PORT_MASK		(7<<28)
-#define  TRANS_DDI_SELECT_PORT(x)	((x)<<28)
-#define  TRANS_DDI_PORT_NONE		(0<<28)
+#if CONFIG(INTEL_GMA_VERSION_2)
+#define  TRANS_DDI_PORT_SHIFT		27
+#define  TRANS_DDI_PORT_WIDTH		0xf
+#define  TRANS_DDI_SELECT_PORT(x)	(((x) + 1) << TRANS_DDI_PORT_SHIFT)
+#else
+#define  TRANS_DDI_PORT_SHIFT		28
+#define  TRANS_DDI_PORT_WIDTH		7
+#define  TRANS_DDI_SELECT_PORT(x)	((x) << TRANS_DDI_PORT_SHIFT)
+#endif
+#define  TRANS_DDI_PORT_MASK		(TRANS_DDI_PORT_WIDTH << TRANS_DDI_PORT_SHIFT)
+#define  TRANS_DDI_PORT_NONE		(0 << TRANS_DDI_PORT_SHIFT)
 #define  TRANS_DDI_MODE_SELECT_MASK	(7<<24)
 #define  TRANS_DDI_MODE_SELECT_HDMI	(0<<24)
 #define  TRANS_DDI_MODE_SELECT_DVI	(1<<24)