tree 8011a5acd782dc0aeedb7ed8383a0848b4fd5019
parent 26d54b70e2821ea383862cc7795b669dde80ca43
author Felix Held <felix-coreboot@felixheld.de> 1679686989 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1680303353 +0000

soc/amd/common/block/cpu/tsc/Makefile: order targets by stage

Now that only one build target per stage is included in the build
depending on CONFIG_SOC_AMD_COMMON_BLOCK_TSC being set, don't use a
separate ifeq block for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9e551b37707081eb2ea1d682013f57c7ca8aabd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74017
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>